{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,13]],"date-time":"2026-06-13T12:47:51Z","timestamp":1781354871093,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":90,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T00:00:00Z","timestamp":1634428800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["1764000"],"award-info":[{"award-number":["1764000"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"DARPA","award":["FA8650-18-2-7862"],"award-info":[{"award-number":["FA8650-18-2-7862"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,10,18]]},"DOI":"10.1145\/3466752.3480065","type":"proceedings-article","created":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T19:16:55Z","timestamp":1634498215000},"page":"350-365","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs"],"prefix":"10.1145","author":[{"given":"Joseph","family":"Zuckerman","sequence":"first","affiliation":[{"name":"Columbia University, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Davide","family":"Giri","sequence":"additional","affiliation":[{"name":"Columbia University, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jihye","family":"Kwon","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paolo","family":"Mantovani","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luca P.","family":"Carloni","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,10,17]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00031"},{"key":"e_1_3_2_1_2_1","unstructured":"ARM. [n. d.]. CoreLink Interconnect. https:\/\/developer.arm.com\/ip-products\/system-ip\/corelink-interconnect.  ARM. [n. d.]. CoreLink Interconnect. https:\/\/developer.arm.com\/ip-products\/system-ip\/corelink-interconnect."},{"key":"e_1_3_2_1_3_1","unstructured":"ARM. 2020. AMBA AXI and ACE Protocol Specification. https:\/\/developer.arm.com\/documentation\/ihi0022\/h.  ARM. 2020. AMBA AXI and ACE Protocol Specification. https:\/\/developer.arm.com\/documentation\/ihi0022\/h."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872414"},{"key":"e_1_3_2_1_5_1","unstructured":"Kevin Barker Thomas Benson Dan Campbell David Ediger Roberto Gioiosa Adolfy Hoisie Darren Kerbyson Joseph Manzano Andres Marquez Leon Song Nathan Tallent and Antonino Tumeo. 2013. PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. Pacific Northwest National Laboratory and Georgia Tech Research Institute.  Kevin Barker Thomas Benson Dan Campbell David Ediger Roberto Gioiosa Adolfy Hoisie Darren Kerbyson Joseph Manzano Andres Marquez Leon Song Nathan Tallent and Antonino Tumeo. 2013. PERFECT (Power Efficiency Revolution For Embedded Computing Technologies) Benchmark Suite Manual. Pacific Northwest National Laboratory and Georgia Tech Research Institute."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3370748.3406564"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2019.2910521"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2013.2280090"},{"key":"e_1_3_2_1_9_1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC). 17:1\u201317:6.","author":"Carloni P.","year":"2016","unstructured":"Luca\u00a0 P. Carloni . 2016 . The Case for Embedded Scalable Platforms . In Proceedings of the ACM\/IEEE Design Automation Conference (DAC). 17:1\u201317:6. Luca\u00a0P. Carloni. 2016. The Case for Embedded Scalable Platforms. In Proceedings of the ACM\/IEEE Design Automation Conference (DAC). 17:1\u201317:6."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3338698.3338893"},{"key":"e_1_3_2_1_11_1","volume-title":"Easing Heterogeneous Cache Coherent SoC Design using Arteris Ncore Interconnect IP","author":"Case Loyd","year":"2016","unstructured":"Loyd Case . 2016. Easing Heterogeneous Cache Coherent SoC Design using Arteris Ncore Interconnect IP . The Linley Group ( 2016 ). Loyd Case. 2016. Easing Heterogeneous Cache Coherent SoC Design using Arteris Ncore Interconnect IP. The Linley Group (2016)."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554787"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3387902.3392631"},{"key":"e_1_3_2_1_14_1","unstructured":"CCIX Consortium. 2018. CCIX Base Specification 1.0. https:\/\/www.ccixconsortium.com\/library\/specification\/.  CCIX Consortium. 2018. CCIX Base Specification 1.0. https:\/\/www.ccixconsortium.com\/library\/specification\/."},{"key":"e_1_3_2_1_15_1","unstructured":"CCIX Consortium. 2019. An Introduction to CCIX. https:\/\/www.ccixconsortium.com\/wp-content\/uploads\/2019\/11\/CCIX-White-Paper-Rev111219.pdf.  CCIX Consortium. 2019. An Introduction to CCIX. https:\/\/www.ccixconsortium.com\/wp-content\/uploads\/2019\/11\/CCIX-White-Paper-Rev111219.pdf."},{"key":"e_1_3_2_1_16_1","volume-title":"Proceedings of the IEEE International Conference on Computer Design (ICCD). 169\u2013176","author":"Chen Y.","year":"2013","unstructured":"Y. Chen , J. Cong , M.\u00a0 A. Ghodrat , M. Huang , C. Liu , B. Xiao , and Y. Zou . 2013. Accelerator-rich CMPs: From concept to real hardware . In Proceedings of the IEEE International Conference on Computer Design (ICCD). 169\u2013176 . https:\/\/doi.org\/10.1109\/ICCD. 2013 .6657039 10.1109\/ICCD.2013.6657039 Y. Chen, J. Cong, M.\u00a0A. Ghodrat, M. Huang, C. Liu, B. Xiao, and Y. Zou. 2013. Accelerator-rich CMPs: From concept to real hardware. In Proceedings of the IEEE International Conference on Computer Design (ICCD). 169\u2013176. https:\/\/doi.org\/10.1109\/ICCD.2013.6657039"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"e_1_3_2_1_18_1","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). 155\u2013166","author":"Choi B.","year":"2011","unstructured":"B. Choi , R. Komuravelli , H. Sung , R. Smolinski , N. Honarmand , S.\u00a0 V. Adve , V.\u00a0 S. Adve , N.\u00a0 P. Carter , and C. Chou . 2011. DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). 155\u2013166 . https:\/\/doi.org\/10.1109\/PACT. 2011 .21 10.1109\/PACT.2011.21 B. Choi, R. Komuravelli, H. Sung, R. Smolinski, N. Honarmand, S.\u00a0V. Adve, V.\u00a0S. Adve, N.\u00a0P. Carter, and C. Chou. 2011. DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). 155\u2013166. https:\/\/doi.org\/10.1109\/PACT.2011.21"},{"key":"e_1_3_2_1_19_1","unstructured":"Cobham Gaisler. [n. d.]. LEON3 Processor. www.gaisler.com\/index.php\/products\/processors\/leon3.  Cobham Gaisler. [n. d.]. LEON3 Processor. www.gaisler.com\/index.php\/products\/processors\/leon3."},{"key":"e_1_3_2_1_20_1","unstructured":"Columbia SLD Group. 2019. ESP Release. www.esp.cs.columbia.edu.  Columbia SLD Group. 2019. ESP Release. www.esp.cs.columbia.edu."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2596667"},{"key":"e_1_3_2_1_22_1","volume-title":"Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization. In 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). 338\u2013343","author":"Cong Thanh","year":"2021","unstructured":"Thanh Cong and Francois Charot . 2021 . Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization. In 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). 338\u2013343 . Thanh Cong and Francois Charot. 2021. Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization. In 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). 338\u2013343."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744794"},{"key":"e_1_3_2_1_24_1","unstructured":"CXL Consortium. 2020. Compute Express Linx 2.0 White Paper. https:\/\/www.computeexpresslink.org\/resource-library.  CXL Consortium. 2020. Compute Express Linx 2.0 White Paper. https:\/\/www.computeexpresslink.org\/resource-library."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/3361682"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3326633"},{"key":"e_1_3_2_1_27_1","volume-title":"Nvidia\u2019s Xavier SoC. In Hot Chips: A Symposium on High Performance Chips.","author":"Ditty Michael","year":"2018","unstructured":"Michael Ditty , Ashish Karandikar , and David Reed . 2018 . Nvidia\u2019s Xavier SoC. In Hot Chips: A Symposium on High Performance Chips. Michael Ditty, Ashish Karandikar, and David Reed. 2018. Nvidia\u2019s Xavier SoC. In Hot Chips: A Symposium on High Performance Chips."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358312"},{"key":"e_1_3_2_1_29_1","volume-title":"Proceedings of the ACM\/IEEE Design Automation Conference (DAC). 966\u2013971","author":"Fajardo F.","unstructured":"C.\u00a0 F. Fajardo , Z. Fang , R. Iyer , G.\u00a0 F. Garcia , S.\u00a0 E. Lee , and L. Zhao . 2011. Buffer-Integrated-Cache: A cost-effective SRAM architecture for handheld and embedded platforms . In Proceedings of the ACM\/IEEE Design Automation Conference (DAC). 966\u2013971 . C.\u00a0F. Fajardo, Z. Fang, R. Iyer, G.\u00a0F. Garcia, S.\u00a0E. Lee, and L. Zhao. 2011. Buffer-Integrated-Cache: A cost-effective SRAM architecture for handheld and embedded platforms. In Proceedings of the ACM\/IEEE Design Automation Conference (DAC). 966\u2013971."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2009.2036980"},{"key":"e_1_3_2_1_31_1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 937\u2013950","author":"Fujiki D.","year":"2020","unstructured":"D. Fujiki , S. Wu , N. Ozog , K. Goliya , D. Blaauw , S. Narayanasamy , and R. Das . 2020. SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space . In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 937\u2013950 . https:\/\/doi.org\/10.1109\/MICRO50266. 2020 .00080 10.1109\/MICRO50266.2020.00080 D. Fujiki, S. Wu, N. Ozog, K. Goliya, D. Blaauw, S. Narayanasamy, and R. Das. 2020. SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space. In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 937\u2013950. https:\/\/doi.org\/10.1109\/MICRO50266.2020.00080"},{"key":"e_1_3_2_1_32_1","unstructured":"Gen-Z Consortium. 2020. Gen-Z Specification 1.1. https:\/\/genzconsortium.org\/specifications\/.  Gen-Z Consortium. 2020. Gen-Z Specification 1.1. https:\/\/genzconsortium.org\/specifications\/."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3073893"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116317"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2877288"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2018.8512153"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3288755"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2019.2892151"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.30"},{"key":"e_1_3_2_1_40_1","volume-title":"Hill and Vijay\u00a0Janapa Reddi","author":"D.","year":"2020","unstructured":"Mark\u00a0 D. Hill and Vijay\u00a0Janapa Reddi . 2020 . Accelerator-level Parallelism . arxiv:cs.DC\/1907.02064 Mark\u00a0D. Hill and Vijay\u00a0Janapa Reddi. 2020. Accelerator-level Parallelism. arxiv:cs.DC\/1907.02064"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.5555\/1622737.1622748"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816019"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.8"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750421"},{"key":"e_1_3_2_1_46_1","unstructured":"Andreas Kurth Wolfgang R\u00f6nninger Thomas Benz Matheus Cavalcante Fabian Schuiki Florian Zaruba and Luca Benini. 2020. An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. arXiv:2009.05334. arxiv:cs.AR\/arXiv:2009.05334  Andreas Kurth Wolfgang R\u00f6nninger Thomas Benz Matheus Cavalcante Fabian Schuiki Florian Zaruba and Luca Benini. 2020. An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication. arXiv:2009.05334. arxiv:cs.AR\/arXiv:2009.05334"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3173162.3173176"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/1455650.1455651"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2807591.2807606"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751237"},{"key":"e_1_3_2_1_51_1","volume-title":"Proceedings of the IEEE Conference on Design, Automation, and Test in Europe (DATE). 602\u2013605","author":"Liu Wei","year":"2010","unstructured":"Wei Liu , Ying Tan , and Qinru Qiu . 2010 . Enhanced Q-Learning Algorithm for Dynamic Power Management with Performance Constraint . In Proceedings of the IEEE Conference on Design, Automation, and Test in Europe (DATE). 602\u2013605 . Wei Liu, Ying Tan, and Qinru Qiu. 2010. Enhanced Q-Learning Algorithm for Dynamic Power Management with Performance Constraint. In Proceedings of the IEEE Conference on Design, Automation, and Test in Europe (DATE). 602\u2013605."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/2086696.2086727"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/2968455.2968509"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415753"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/71.113080"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00055"},{"key":"e_1_3_2_1_57_1","unstructured":"Mobileye (an Intel Company). 2018. Towards Autonomous Driving. https:\/\/s21.q4cdn.com\/600692695\/files\/doc_presentations\/2018\/CES-2018-final-MBLY.pdf. CES.  Mobileye (an Intel Company). 2018. Towards Autonomous Driving. https:\/\/s21.q4cdn.com\/600692695\/files\/doc_presentations\/2018\/CES-2018-final-MBLY.pdf. CES."},{"key":"e_1_3_2_1_58_1","volume-title":"A Primer on Memory Consistency and Cache Coherence","author":"Nagarajan V.","unstructured":"V. Nagarajan , D.\u00a0 J. Sorin , M.\u00a0 D. Hill , and D.\u00a0 A. Wood . 2020. A Primer on Memory Consistency and Cache Coherence : Second Edition. Morgan & Claypool . V. Nagarajan, D.\u00a0J. Sorin, M.\u00a0D. Hill, and D.\u00a0A. Wood. 2020. A Primer on Memory Consistency and Cache Coherence: Second Edition. Morgan & Claypool."},{"key":"e_1_3_2_1_59_1","volume-title":"Information and Communication Technology for Intelligent Systems (ICTIS 2017) -","author":"Nayak J","unstructured":"Rikin\u00a0 J Nayak and Jaiminkumar\u00a0 B Chavda . 2018. Comparison of accelerator coherency port (ACP) and high performance port (HP) for data transfer in DDR memory Using Xilinx ZYNQ SoC . In Information and Communication Technology for Intelligent Systems (ICTIS 2017) - Volume 1 . Springer , 94\u2013102. Rikin\u00a0J Nayak and Jaiminkumar\u00a0B Chavda. 2018. Comparison of accelerator coherency port (ACP) and high performance port (HP) for data transfer in DDR memory Using Xilinx ZYNQ SoC. In Information and Communication Technology for Intelligent Systems (ICTIS 2017) - Volume 1. Springer, 94\u2013102."},{"key":"e_1_3_2_1_60_1","unstructured":"NVIDIA. 2017. NVIDIA Deep Learning Accelerator (NVDLA). www.nvdla.org.  NVIDIA. 2017. NVIDIA Deep Learning Accelerator (NVDLA). www.nvdla.org."},{"key":"e_1_3_2_1_61_1","unstructured":"OpenCAPI Consortium. 2016. OpenCAPI 4.0 Specifications. https:\/\/opencapi.org\/technical\/specifications\/.  OpenCAPI Consortium. 2016. OpenCAPI 4.0 Specifications. https:\/\/opencapi.org\/technical\/specifications\/."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080254"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304025"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2996145"},{"key":"e_1_3_2_1_65_1","volume-title":"Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). 58\u201370","author":"Qin E.","year":"2020","unstructured":"E. Qin , A. Samajdar , H. Kwon , V. Nadella , S. Srinivasan , D. Das , B. Kaul , and T. Krishna . 2020. SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training . In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). 58\u201370 . https:\/\/doi.org\/10.1109\/HPCA47549. 2020 .00015 10.1109\/HPCA47549.2020.00015 E. Qin, A. Samajdar, H. Kwon, V. Nadella, S. Srinivasan, D. Das, B. Kaul, and T. Krishna. 2020. SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training. In Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA). 58\u201370. https:\/\/doi.org\/10.1109\/HPCA47549.2020.00015"},{"key":"e_1_3_2_1_66_1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 908\u2013921","author":"Rahman S.","year":"2020","unstructured":"S. Rahman , N. Abu-Ghazaleh , and R. Gupta . 2020. GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing . In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 908\u2013921 . https:\/\/doi.org\/10.1109\/MICRO50266. 2020 .00078 10.1109\/MICRO50266.2020.00078 S. Rahman, N. Abu-Ghazaleh, and R. Gupta. 2020. GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing. In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 908\u2013921. https:\/\/doi.org\/10.1109\/MICRO50266.2020.00078"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983050"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/2513683.2513688"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2014.2320556"},{"key":"e_1_3_2_1_70_1","unstructured":"Yakun\u00a0Sophia Shao and David Brooks. 2015. Research Infrastructures for Hardware Accelerators. Morgan & Claypool.  Yakun\u00a0Sophia Shao and David Brooks. 2015. Research Infrastructures for Hardware Accelerators. Morgan & Claypool."},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358302"},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783751"},{"key":"e_1_3_2_1_73_1","first-page":"1","volume-title":"Proceedings of the GNU Radio Conference 4","author":"Sisbot E","year":"2019","unstructured":"E Sisbot , Augusto Vega , Arun Paidimarri , John-David Wellman , Alper Buyuktosunoglu , Pradip Bose , and David Trilla . 2019 . Multi-Vehicle Map Fusion using GNU Radio . Proceedings of the GNU Radio Conference 4 , 1 (2019). E Sisbot, Augusto Vega, Arun Paidimarri, John-David Wellman, Alper Buyuktosunoglu, Pradip Bose, and David Trilla. 2019. Multi-Vehicle Map Fusion using GNU Radio. Proceedings of the GNU Radio Conference 4, 1 (2019)."},{"key":"e_1_3_2_1_74_1","unstructured":"Stephanie Soldavini and Christian Pilato. 2021. A Survey on Domain-Specific Memory Architectures. arXiv preprint arXiv:2108.08672(2021).  Stephanie Soldavini and Christian Pilato. 2021. A Survey on Domain-Specific Memory Architectures. arXiv preprint arXiv:2108.08672(2021)."},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"crossref","unstructured":"Daniel\u00a0J. Sorin Mark\u00a0D. Hill and David\u00a0A. Wood. 2011. A Primer on Memory Consistency and Cache Coherence. Morgan & Claypool.  Daniel\u00a0J. Sorin Mark\u00a0D. Hill and David\u00a0A. Wood. 2011. A Primer on Memory Consistency and Cache Coherence. Morgan & Claypool.","DOI":"10.1007\/978-3-031-01733-9"},{"key":"e_1_3_2_1_76_1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 766\u2013780","author":"Srivastava N.","year":"2020","unstructured":"N. Srivastava , H. Jin , J. Liu , D. Albonesi , and Z. Zhang . 2020. MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product . In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 766\u2013780 . https:\/\/doi.org\/10.1109\/MICRO50266. 2020 .00068 10.1109\/MICRO50266.2020.00068 N. Srivastava, H. Jin, J. Liu, D. Albonesi, and Z. Zhang. 2020. MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product. In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 766\u2013780. https:\/\/doi.org\/10.1109\/MICRO50266.2020.00068"},{"key":"e_1_3_2_1_77_1","volume-title":"CoreLink Intelligent System IP by ARM","author":"Stevens Ashley","year":"2011","unstructured":"Ashley Stevens . 2011. Introduction to AMBA\u00ae 4 ACE and big.LITTLE Processing Technology. ARM White Paper , CoreLink Intelligent System IP by ARM ( 2011 ). Ashley Stevens. 2011. Introduction to AMBA\u00ae 4 ACE and big.LITTLE Processing Technology. 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IBM Journal of Research and Development(2015).","author":"Stuecheli Jeffrey","year":"2015","unstructured":"Jeffrey Stuecheli , Bart Blaner , C.\u00a0 R. Johns , and M.\u00a0 S. Siegel . 2015 . CAPI: A Coherent Accelerator Processor Interface. IBM Journal of Research and Development(2015). Jeffrey Stuecheli, Bart Blaner, C.\u00a0R. Johns, and M.\u00a0S. Siegel. 2015. CAPI: A Coherent Accelerator Processor Interface. IBM Journal of Research and Development(2015)."},{"key":"e_1_3_2_1_80_1","volume-title":"Reinforcement Learning: An Introduction","author":"Sutton S.","year":"2018","unstructured":"Richard\u00a0 S. Sutton and Andrew\u00a0 G. Barto . 2018 . Reinforcement Learning: An Introduction . MIT press . Richard\u00a0S. Sutton and Andrew\u00a0G. Barto. 2018. Reinforcement Learning: An Introduction. MIT press."},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"crossref","unstructured":"Thierry Tambe Coleman Hooper Lillian Pentecost Tianyu Jia En-Yu Yang Marco Donato Victor Sanh Paul\u00a0N. Whatmough Alexander\u00a0M. Rush David Brooks and Gu-Yeon Wei. 2021. EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference. arxiv:cs.AR\/2011.14203  Thierry Tambe Coleman Hooper Lillian Pentecost Tianyu Jia En-Yu Yang Marco Donato Victor Sanh Paul\u00a0N. Whatmough Alexander\u00a0M. Rush David Brooks and Gu-Yeon Wei. 2021. EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference. arxiv:cs.AR\/2011.14203","DOI":"10.1145\/3466752.3480095"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983043"},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1145\/2716282.2716283"},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF00992698"},{"key":"e_1_3_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541961"},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691165"},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056023"},{"key":"e_1_3_2_1_89_1","volume-title":"Hot Chips Symposium.","year":"2018","unstructured":"Xilinx. 2018 . Adaptable Intelligence: The Next Computing Era. Keynote , Hot Chips Symposium. Xilinx. 2018. Adaptable Intelligence: The Next Computing Era. Keynote, Hot Chips Symposium."},{"key":"e_1_3_2_1_90_1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 895\u2013907","author":"Yao P.","year":"2020","unstructured":"P. Yao , L. Zheng , Z. Zeng , Y. Huang , C. Gui , X. Liao , H. Jin , and J. Xue . 2020. A Locality-Aware Energy-Efficient Accelerator for Graph Mining Applications . In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 895\u2013907 . https:\/\/doi.org\/10.1109\/MICRO50266. 2020 .00077 10.1109\/MICRO50266.2020.00077 P. Yao, L. Zheng, Z. Zeng, Y. Huang, C. Gui, X. Liao, H. Jin, and J. Xue. 2020. A Locality-Aware Energy-Efficient Accelerator for Graph Mining Applications. In Proceedings of the IEEE\/ACM International Symposium on Microarchitecture (MICRO). 895\u2013907. https:\/\/doi.org\/10.1109\/MICRO50266.2020.00077"},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317768"}],"event":{"name":"MICRO '21: 54th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Virtual Event Greece","acronym":"MICRO '21","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480065","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3466752.3480065","content-type":"text\/html","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480065","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480065","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:24:53Z","timestamp":1750195493000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480065"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,17]]},"references-count":90,"alternative-id":["10.1145\/3466752.3480065","10.1145\/3466752"],"URL":"https:\/\/doi.org\/10.1145\/3466752.3480065","relation":{},"subject":[],"published":{"date-parts":[[2021,10,17]]},"assertion":[{"value":"2021-10-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}