{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:20:05Z","timestamp":1750220405049,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":50,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T00:00:00Z","timestamp":1634428800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,10,18]]},"DOI":"10.1145\/3466752.3480075","type":"proceedings-article","created":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T19:16:55Z","timestamp":1634498215000},"page":"86-99","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["COSPlay: Leveraging Task-Level Parallelism for High-Throughput Synchronous Persistence"],"prefix":"10.1145","author":[{"given":"Marina","family":"Vemmou","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, United States of America"}]},{"given":"Alexandros","family":"Daglis","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, United States of America"}]}],"member":"320","published-online":{"date-parts":[[2021,10,17]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00044"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3015146"},{"key":"e_1_3_2_1_3_1","unstructured":"boost-coroutines [n.d.]. Performance of coroutine switching in the Boost 1.74.0 C++ library. https:\/\/www.boost.org\/doc\/libs\/1_74_0\/libs\/context\/doc\/html\/context\/performance.html  boost-coroutines [n.d.]. Performance of coroutine switching in the Boost 1.74.0 C++ library. https:\/\/www.boost.org\/doc\/libs\/1_74_0\/libs\/context\/doc\/html\/context\/performance.html"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2660193.2660224"},{"key":"e_1_3_2_1_5_1","unstructured":"co2 [n.d.]. CO2 - Coroutine II: A C++ await\/yield emulation library for stackless coroutine. https:\/\/github.com\/jamboree\/co2  co2 [n.d.]. CO2 - Coroutine II: A C++ await\/yield emulation library for stackless coroutine. https:\/\/github.com\/jamboree\/co2"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629575.1629589"},{"key":"e_1_3_2_1_8_1","unstructured":"cpp-coroutines [n.d.]. Coroutines in C++20. https:\/\/en.cppreference.com\/w\/cpp\/language\/coroutines  cpp-coroutines [n.d.]. Coroutines in C++20. https:\/\/en.cppreference.com\/w\/cpp\/language\/coroutines"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378481"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192367"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00060"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3180270.3180275"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358321"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378472"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.14778\/3430915.3430932"},{"key":"e_1_3_2_1_16_1","volume-title":"Proceedings of the 2017 EuroSys Conference. 468\u2013482","author":"Ching-Hsiang Hsu Terry","year":"2017","unstructured":"Terry Ching-Hsiang Hsu , Helge Br\u00fcgner , Indrajit Roy , Kimberly Keeton , and Patrick Eugster . 2017 . NVthreads: Practical Persistence for Multi-threaded Applications . In Proceedings of the 2017 EuroSys Conference. 468\u2013482 . Terry Ching-Hsiang Hsu, Helge Br\u00fcgner, Indrajit Roy, Kimberly Keeton, and Patrick Eugster. 2017. NVthreads: Practical Persistence for Multi-threaded Applications. In Proceedings of the 2017 EuroSys Conference. 468\u2013482."},{"key":"e_1_3_2_1_17_1","unstructured":"Intel [n.d.]. Intel Cascade Lake Microarchitecture. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/cascade_lake  Intel [n.d.]. Intel Cascade Lake Microarchitecture. https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/cascade_lake"},{"key":"e_1_3_2_1_18_1","unstructured":"Intel Corporation. 2020. Intel\u00ae architecture instruction set extensions and future features programming reference.https:\/\/www.intel.com\/content\/www\/us\/en\/products\/memory-storage\/optane-dc-persistent-memory.html  Intel Corporation. 2020. Intel\u00ae architecture instruction set extensions and future features programming reference.https:\/\/www.intel.com\/content\/www\/us\/en\/products\/memory-storage\/optane-dc-persistent-memory.html"},{"key":"e_1_3_2_1_19_1","unstructured":"Joseph Izraelevitz Jian Yang Lu Zhang Juno Kim Xiao Liu Amirsaman Memaripour Yun\u00a0Joon Soh Zixuan Wang Yi Xu Subramanya\u00a0R. Dulloor Jishen Zhao and Steven Swanson. 2019. Basic Performance Measurements of the Intel Optane DC Persistent Memory Module. CoRR abs\/1903.05714(2019).  Joseph Izraelevitz Jian Yang Lu Zhang Juno Kim Xiao Liu Amirsaman Memaripour Yun\u00a0Joon Soh Zixuan Wang Yi Xu Subramanya\u00a0R. Dulloor Jishen Zhao and Steven Swanson. 2019. Basic Performance Measurements of the Intel Optane DC Persistent Memory Module. CoRR abs\/1903.05714(2019)."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.14778\/3236187.3236216"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830805"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.50"},{"key":"e_1_3_2_1_23_1","volume-title":"Proceedings of the 12th Symposium on Operating System Design and Implementation (OSDI). 185\u2013201","author":"Kalia Anuj","year":"2016","unstructured":"Anuj Kalia , Michael Kaminsky , and David\u00a0 G. Andersen . 2016 . FaSST: Fast, Scalable and Simple Distributed Transactions with Two-Sided (RDMA) Datagram RPCs . In Proceedings of the 12th Symposium on Operating System Design and Implementation (OSDI). 185\u2013201 . Anuj Kalia, Michael Kaminsky, and David\u00a0G. Andersen. 2016. FaSST: Fast, Scalable and Simple Distributed Transactions with Two-Sided (RDMA) Datagram RPCs. In Proceedings of the 12th Symposium on Operating System Design and Implementation (OSDI). 185\u2013201."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080229"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195709"},{"key":"e_1_3_2_1_26_1","unstructured":"Chuanpeng Li Chen Ding and Kai Shen. 2007. Quantifying the cost of context switch. In Experimental Computer Science. 2.  Chuanpeng Li Chen Ding and Kai Shen. 2007. Quantifying the cost of context switch. In Experimental Computer Science. 2."},{"key":"e_1_3_2_1_27_1","volume-title":"Fence Scoping. In Proceedings of the 2014 ACM\/IEEE Conference on Supercomputing (SC). 105\u2013116","author":"Lin Changhui","year":"2014","unstructured":"Changhui Lin , Vijay Nagarajan , and Rajiv Gupta . 2014 . Fence Scoping. In Proceedings of the 2014 ACM\/IEEE Conference on Supercomputing (SC). 105\u2013116 . Changhui Lin, Vijay Nagarajan, and Rajiv Gupta. 2014. Fence Scoping. In Proceedings of the 2014 ACM\/IEEE Conference on Supercomputing (SC). 105\u2013116."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037714"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322206"},{"key":"e_1_3_2_1_30_1","volume-title":"Proceedings of the 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 539\u2013554","author":"Mahdizadeh-Shahri Sara","year":"2020","unstructured":"Sara Mahdizadeh-Shahri , Seyed\u00a0Armin Vakil-Ghahani , and Aasheesh Kolli . 2020 . (Almost) Fence-less Persist Ordering . In Proceedings of the 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 539\u2013554 . Sara Mahdizadeh-Shahri, Seyed\u00a0Armin Vakil-Ghahani, and Aasheesh Kolli. 2020. (Almost) Fence-less Persist Ordering. In Proceedings of the 53rd Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 539\u2013554."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378456"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037730"},{"key":"e_1_3_2_1_33_1","volume-title":"Proceedings of the 2015 USENIX Annual Technical Conference (ATC). 291\u2013305","author":"Nelson Jacob","year":"2015","unstructured":"Jacob Nelson , Brandon Holt , Brandon Myers , Preston Briggs , Luis Ceze , Simon Kahan , and Mark Oskin . 2015 . Latency-Tolerant Software Distributed Shared Memory . In Proceedings of the 2015 USENIX Annual Technical Conference (ATC). 291\u2013305 . Jacob Nelson, Brandon Holt, Brandon Myers, Preston Briggs, Luis Ceze, Simon Kahan, and Mark Oskin. 2015. Latency-Tolerant Software Distributed Shared Memory. In Proceedings of the 2015 USENIX Annual Technical Conference (ATC). 291\u2013305."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00048"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3319647.3325827"},{"key":"e_1_3_2_1_36_1","unstructured":"optane [n.d.]. Intel Optane DC Persistent Memory. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/memory-storage\/optane-dc-persistent-memory.html  optane [n.d.]. Intel Optane DC Persistent Memory. https:\/\/www.intel.com\/content\/www\/us\/en\/products\/memory-storage\/optane-dc-persistent-memory.html"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853222"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.14778\/3149193.3149202"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3329785.3329917"},{"key":"e_1_3_2_1_40_1","unstructured":"J.P. Shen and M.H. Lipasti. 2013. Modern Processor Design: Fundamentals of Superscalar Processors. Waveland Press.  J.P. Shen and M.H. Lipasti. 2013. Modern Processor Design: Fundamentals of Superscalar Processors. Waveland Press."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124539"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080240"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.5555\/956417.956575"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485963"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"crossref","unstructured":"Dan Tsafrir. 2007. The context-switch overhead inflicted by hardware interrupts (and the enigma of do-nothing loops). In Experimental Computer Science. 4.  Dan Tsafrir. 2007. The context-switch overhead inflicted by hardware interrupts (and the enigma of do-nothing loops). In Experimental Computer Science. 4.","DOI":"10.1145\/1281700.1281704"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1007\/s00778-020-00622-9"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"e_1_3_2_1_48_1","volume-title":"Proceedings of the 13th Symposium on Operating System Design and Implementation (OSDI). 233\u2013251","author":"Wei Xingda","year":"2018","unstructured":"Xingda Wei , Zhiyuan Dong , Rong Chen , and Haibo Chen . 2018 . Deconstructing RDMA-enabled Distributed Transactions: Hybrid is Better! . In Proceedings of the 13th Symposium on Operating System Design and Implementation (OSDI). 233\u2013251 . Xingda Wei, Zhiyuan Dong, Rong Chen, and Haibo Chen. 2018. Deconstructing RDMA-enabled Distributed Transactions: Hybrid is Better!. In Proceedings of the 13th Symposium on Operating System Design and Implementation (OSDI). 233\u2013251."},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00043"}],"event":{"name":"MICRO '21: 54th Annual IEEE\/ACM International Symposium on Microarchitecture","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"],"location":"Virtual Event Greece","acronym":"MICRO '21"},"container-title":["MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480075","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480075","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:18:56Z","timestamp":1750191536000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480075"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,17]]},"references-count":50,"alternative-id":["10.1145\/3466752.3480075","10.1145\/3466752"],"URL":"https:\/\/doi.org\/10.1145\/3466752.3480075","relation":{},"subject":[],"published":{"date-parts":[[2021,10,17]]},"assertion":[{"value":"2021-10-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}