{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T15:08:30Z","timestamp":1781622510321,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":60,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T00:00:00Z","timestamp":1634428800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100002858","name":"China Postdoctoral Science Foundation","doi-asserted-by":"publisher","award":["2020M680568,2021T140376"],"award-info":[{"award-number":["2020M680568,2021T140376"]}],"id":[{"id":"10.13039\/501100002858","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Zhejiang Lab Grant","award":["2020KC0AB03"],"award-info":[{"award-number":["2020KC0AB03"]}]},{"name":"National Key Research & Development Program of China","award":["2018YFB1003301"],"award-info":[{"award-number":["2018YFB1003301"]}]},{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2011146,1738783,1910413,1718080"],"award-info":[{"award-number":["2011146,1738783,1910413,1718080"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61832011?62022051?61772300?61877035"],"award-info":[{"award-number":["61832011?62022051?61772300?61877035"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,10,18]]},"DOI":"10.1145\/3466752.3480078","type":"proceedings-article","created":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T19:16:55Z","timestamp":1634498215000},"page":"59-70","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":32,"title":["ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory based SSDs"],"prefix":"10.1145","author":[{"given":"Congming","family":"Gao","sequence":"first","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xin","family":"Xin","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Youyou","family":"Lu","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Youtao","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Pittsburgh"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jun","family":"Yang","sequence":"additional","affiliation":[{"name":"University of Pittsburgh, United States of America"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiwu","family":"Shu","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,10,17]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Nitin Agrawal Vijayan Prabhakaran Ted Wobber John\u00a0D Davis Mark\u00a0S Manasse and Rina Panigrahy. 2008. Design tradeoffs for SSD performance.. In ATC. USENIX.  Nitin Agrawal Vijayan Prabhakaran Ted Wobber John\u00a0D Davis Mark\u00a0S Manasse and Rina Panigrahy. 2008. Design tradeoffs for SSD performance.. In ATC. USENIX."},{"key":"e_1_3_2_1_2_1","unstructured":"Junwhan Ahn Sungpack Hong Sungjoo Yoo and etal2015. A scalable processing-in-memory accelerator for parallel graph processing. In ISCA. ACM.  Junwhan Ahn Sungpack Hong Sungjoo Yoo and et al.2015. A scalable processing-in-memory accelerator for parallel graph processing. In ISCA. ACM."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"crossref","unstructured":"Berkin Akin Franz Franchetti and James\u00a0C Hoe. 2015. Data reorganization in memory using 3D-stacked DRAM. In CAN. ACM.  Berkin Akin Franz Franchetti and James\u00a0C Hoe. 2015. Data reorganization in memory using 3D-stacked DRAM. In CAN. ACM.","DOI":"10.1145\/2749469.2750397"},{"key":"e_1_3_2_1_4_1","volume-title":"Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems","author":"Asghari-Moghaddam Hadi","year":"2016","unstructured":"Hadi Asghari-Moghaddam , Young\u00a0Hoon Son , Jung\u00a0Ho Ahn , and Nam\u00a0Sung Kim . 2016 . Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems . In MICRO. IEEE. Hadi Asghari-Moghaddam, Young\u00a0Hoon Son, Jung\u00a0Ho Ahn, and Nam\u00a0Sung Kim. 2016. Chameleon: Versatile and practical near-DRAM acceleration architecture for large memory systems. In MICRO. IEEE."},{"key":"e_1_3_2_1_5_1","volume-title":"Nature","author":"Borghetti Julien","unstructured":"Julien Borghetti , Gregory\u00a0 S Snider , Philip\u00a0 J Kuekes , J\u00a0Joshua Yang , Duncan\u00a0 R Stewart , and R\u00a0Stanley Williams . 2010. \u2018Memristive\u2019switches enable \u2018stateful\u2019logic operations via material implication . In Nature . Nature Publishing Group . Julien Borghetti, Gregory\u00a0S Snider, Philip\u00a0J Kuekes, J\u00a0Joshua Yang, Duncan\u00a0R Stewart, and R\u00a0Stanley Williams. 2010. \u2018Memristive\u2019switches enable \u2018stateful\u2019logic operations via material implication. In Nature. Nature Publishing Group."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/IROS.2000.895274"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2713127"},{"key":"e_1_3_2_1_8_1","unstructured":"Chee-Yong Chan and Yannis\u00a0E Ioannidis. 1998. Bitmap index design and evaluation. In SIGMOD. ACM.  Chee-Yong Chan and Yannis\u00a0E Ioannidis. 1998. Bitmap index design and evaluation. In SIGMOD. ACM."},{"key":"e_1_3_2_1_9_1","volume-title":"CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives.Fast.","author":"Chen Feng","year":"2011","unstructured":"Feng Chen , Tian Luo , and Xiaodong Zhang . 2011 . CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives.Fast. Feng Chen, Tian Luo, and Xiaodong Zhang. 2011. CAFTL: A Content-Aware Flash Translation Layer Enhancing the Lifespan of Flash Memory based Solid State Drives.Fast."},{"key":"e_1_3_2_1_10_1","volume-title":"Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. In ISCA. ACM.","author":"Chi Ping","year":"2016","unstructured":"Ping Chi , Shuangchen Li , Cong Xu , Tao Zhang , Jishen Zhao , Yongpan Liu , Yu Wang , and Yuan Xie . 2016 . Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. In ISCA. ACM. Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory. In ISCA. ACM."},{"key":"e_1_3_2_1_11_1","volume":"201","author":"Do Jaeyoung","unstructured":"Jaeyoung Do , Yang-Suk Kee , Jignesh\u00a0 M Patel , Chanik Park , Kwanghyun Park , and David\u00a0 J DeWitt. 201 3. Query processing on smart ssds: Opportunities and challenges. In SIGMOD. ACM. Jaeyoung Do, Yang-Suk Kee, Jignesh\u00a0M Patel, Chanik Park, Kwanghyun Park, and David\u00a0J DeWitt. 2013. Query processing on smart ssds: Opportunities and challenges. In SIGMOD. ACM.","journal-title":"J DeWitt."},{"key":"e_1_3_2_1_12_1","volume-title":"Neural cache: Bit-serial in-cache acceleration of deep neural networks","author":"Eckert Charles","unstructured":"Charles Eckert , Xiaowei Wang , Jingcheng Wang , Arun Subramaniyan , Ravi Iyer , Dennis Sylvester , David Blaaauw , and Reetuparna Das . 2018. Neural cache: Bit-serial in-cache acceleration of deep neural networks . In ISCA. IEEE. Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi Iyer, Dennis Sylvester, David Blaaauw, and Reetuparna Das. 2018. Neural cache: Bit-serial in-cache acceleration of deep neural networks. In ISCA. IEEE."},{"key":"e_1_3_2_1_13_1","unstructured":"ENC. [n.d.]. Cosmos OpenSSD Platform. http:\/\/www.openssd-project.org\/wiki\/Cosmos_OpenSSD_Platform.  ENC. [n.d.]. Cosmos OpenSSD Platform. http:\/\/www.openssd-project.org\/wiki\/Cosmos_OpenSSD_Platform."},{"key":"e_1_3_2_1_14_1","volume-title":"Hierarchical color image region segmentation for content-based image retrieval system","author":"Fuh Chiou-Shann","unstructured":"Chiou-Shann Fuh , Shun-Wen Cho , and Kai Essig . 2000. Hierarchical color image region segmentation for content-based image retrieval system . In TIP. IEEE. Chiou-Shann Fuh, Shun-Wen Cho, and Kai Essig. 2000. Hierarchical color image region segmentation for content-based image retrieval system. In TIP. IEEE."},{"key":"e_1_3_2_1_15_1","volume-title":"Parallel all the time: Plane level parallelism exploration for high performance SSDs","author":"Gao Congming","unstructured":"Congming Gao , Liang Shi , Chun\u00a0Jason Xue , Cheng Ji , Jun Yang , and Youtao Zhang . 2019. Parallel all the time: Plane level parallelism exploration for high performance SSDs . In MSST. IEEE. Congming Gao, Liang Shi, Chun\u00a0Jason Xue, Cheng Ji, Jun Yang, and Youtao Zhang. 2019. Parallel all the time: Plane level parallelism exploration for high performance SSDs. In MSST. IEEE."},{"key":"e_1_3_2_1_16_1","volume-title":"Exploiting parallelism in I\/O scheduling for access conflict minimization in flash-based solid state drives","author":"Gao Congming","unstructured":"Congming Gao , Liang Shi , Mengying Zhao , Chun\u00a0Jason Xue , Kaijie Wu , and Edwin H-M Sha . 2014. Exploiting parallelism in I\/O scheduling for access conflict minimization in flash-based solid state drives . In MSST. IEEE. Congming Gao, Liang Shi, Mengying Zhao, Chun\u00a0Jason Xue, Kaijie Wu, and Edwin H-M Sha. 2014. Exploiting parallelism in I\/O scheduling for access conflict minimization in flash-based solid state drives. In MSST. IEEE."},{"key":"e_1_3_2_1_17_1","volume-title":"Constructing large, durable and fast SSD system via reprogramming 3D TLC flash memory","author":"Gao Congming","unstructured":"Congming Gao , Min Ye , Qiao Li , Chun\u00a0Jason Xue , Youtao Zhang , Liang Shi , and Jun Yang . 2019. Constructing large, durable and fast SSD system via reprogramming 3D TLC flash memory . In MICRO. IEEE. Congming Gao, Min Ye, Qiao Li, Chun\u00a0Jason Xue, Youtao Zhang, Liang Shi, and Jun Yang. 2019. Constructing large, durable and fast SSD system via reprogramming 3D TLC flash memory. In MICRO. IEEE."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358260"},{"key":"e_1_3_2_1_19_1","volume-title":"Felix: Fast and energy-efficient logic in memory","author":"Gupta Saransh","year":"2018","unstructured":"Saransh Gupta , Mohsen Imani , and Tajana Rosing . 2018 . Felix: Fast and energy-efficient logic in memory . In ICCAD. IEEE. Saransh Gupta, Mohsen Imani, and Tajana Rosing. 2018. Felix: Fast and energy-efficient logic in memory. In ICCAD. IEEE."},{"key":"e_1_3_2_1_20_1","volume-title":"Optical Engineering","author":"Han JongWook","unstructured":"JongWook Han , Choon-Sik Park , Dae-Hyun Ryu , and Eun-Soo Kim . 1999. Optical image encryption based on XOR operations . In Optical Engineering . International Society for Optics and Photonics . JongWook Han, Choon-Sik Park, Dae-Hyun Ryu, and Eun-Soo Kim. 1999. Optical image encryption based on XOR operations. In Optical Engineering. International Society for Optics and Photonics."},{"key":"e_1_3_2_1_21_1","volume-title":"2012. Exploring and exploiting the multilevel parallelism inside SSDs for improved performance and endurance","author":"Hu Yang","unstructured":"Yang Hu , Hong Jiang , Dan Feng , and 2012. Exploring and exploiting the multilevel parallelism inside SSDs for improved performance and endurance . In TC. IEEE. Yang Hu, Hong Jiang, Dan Feng, and et al.2012. Exploring and exploiting the multilevel parallelism inside SSDs for improved performance and endurance. In TC. IEEE."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322237"},{"key":"e_1_3_2_1_23_1","unstructured":"Intel 2015. Intel 64M25 Compute NAND Flash Memory Datasheet. Intel.  Intel 2015. Intel 64M25 Compute NAND Flash Memory Datasheet. Intel."},{"key":"e_1_3_2_1_24_1","volume-title":"2015. A 128 Gb 3b\/cell V-NAND flash memory with 1 Gb\/s I\/O rate","author":"Jeong Woopyo","unstructured":"Woopyo Jeong , Jae-woo Im, Doo-Hyun Kim , and 2015. A 128 Gb 3b\/cell V-NAND flash memory with 1 Gb\/s I\/O rate . In JSSC. IEEE. Woopyo Jeong, Jae-woo Im, Doo-Hyun Kim, and et al.2015. A 128 Gb 3b\/cell V-NAND flash memory with 1 Gb\/s I\/O rate. In JSSC. IEEE."},{"key":"e_1_3_2_1_25_1","volume-title":"Performance analysis of nvme ssd-based all-flash array systems","author":"Jin Young\u00a0Tack","unstructured":"Young\u00a0Tack Jin , Sungjoon Ahn , and Sungjin Lee . 2018. Performance analysis of nvme ssd-based all-flash array systems . In ISPASS. IEEE. Young\u00a0Tack Jin, Sungjoon Ahn, and Sungjin Lee. 2018. Performance analysis of nvme ssd-based all-flash array systems. In ISPASS. IEEE."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"crossref","unstructured":"Dongku Kang Woopyo Jeong Chulbum Kim and etal2016. 256 Gb 3 b\/cell V-NAND flash memory with 48 stacked WL layers. JSSC.  Dongku Kang Woopyo Jeong Chulbum Kim and et al.2016. 256 Gb 3 b\/cell V-NAND flash memory with 48 stacked WL layers. JSSC.","DOI":"10.1109\/ISSCC.2016.7417941"},{"key":"e_1_3_2_1_27_1","volume-title":"SHRD: Improving Spatial Locality in Flash Storage Accesses by Sequentializing in Host and Randomizing in Device. In FAST. USENIX, 271\u2013284.","author":"Kim Hyukjoong","year":"2017","unstructured":"Hyukjoong Kim , Dongkun Shin , Yun\u00a0Ho Jeong , and Kyung\u00a0Ho Kim . 2017 . SHRD: Improving Spatial Locality in Flash Storage Accesses by Sequentializing in Host and Randomizing in Device. In FAST. USENIX, 271\u2013284. Hyukjoong Kim, Dongkun Shin, Yun\u00a0Ho Jeong, and Kyung\u00a0Ho Kim. 2017. SHRD: Improving Spatial Locality in Flash Storage Accesses by Sequentializing in Host and Randomizing in Device. In FAST. USENIX, 271\u2013284."},{"key":"e_1_3_2_1_28_1","unstructured":"Sungchan Kim Hyunok Oh Chanik Park and etal2011. Fast energy efficient scan inside flash memory SSDs. ADMS.  Sungchan Kim Hyunok Oh Chanik Park and et al.2011. Fast energy efficient scan inside flash memory SSDs. ADMS."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","unstructured":"Ricardo Koller and Raju Rangaswami. 2010. I\/O deduplication: Utilizing content similarity to improve I\/O performance. In TOS. ACM.  Ricardo Koller and Raju Rangaswami. 2010. I\/O deduplication: Utilizing content similarity to improve I\/O performance. In TOS. ACM.","DOI":"10.1145\/1837915.1837921"},{"key":"e_1_3_2_1_30_1","volume-title":"2017. Summarizer: trading communication with computing near storage","author":"Koo Gunjae","unstructured":"Gunjae Koo , Kiran\u00a0Kumar Matam , I Te , and 2017. Summarizer: trading communication with computing near storage . In MICRO. IEEE. Gunjae Koo, Kiran\u00a0Kumar Matam, I Te, and et al.2017. Summarizer: trading communication with computing near storage. In MICRO. IEEE."},{"key":"e_1_3_2_1_31_1","unstructured":"Joo\u00a0Hwan Lee Hui Zhang Veronica Lagrange and etal2020. SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD. CAL.  Joo\u00a0Hwan Lee Hui Zhang Veronica Lagrange and et al.2020. SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD. CAL."},{"key":"e_1_3_2_1_32_1","volume-title":"2016. 7.5 A 128Gb 2b\/cell NAND flash memory in 14nm technology with tPROG= 640\u03bcs and 800MB\/s I\/O rate","author":"Lee Seungjae","unstructured":"Seungjae Lee , Jin-yub Lee, Il-han Park, and 2016. 7.5 A 128Gb 2b\/cell NAND flash memory in 14nm technology with tPROG= 640\u03bcs and 800MB\/s I\/O rate . In ISSCC. IEEE. Seungjae Lee, Jin-yub Lee, Il-han Park, and et al.2016. 7.5 A 128Gb 2b\/cell NAND flash memory in 14nm technology with tPROG= 640\u03bcs and 800MB\/s I\/O rate. In ISSCC. IEEE."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"e_1_3_2_1_34_1","unstructured":"Xiaofan Lin Cong Zhao and Wei Pan. 2017. Towards accurate binary convolutional neural network. arXiv preprint arXiv:1711.11294.  Xiaofan Lin Cong Zhao and Wei Pan. 2017. Towards accurate binary convolutional neural network. arXiv preprint arXiv:1711.11294."},{"key":"e_1_3_2_1_35_1","unstructured":"Kevin Marks. 2013. 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Parallel NAND System Power Calculator. https:\/\/www.micron.com\/support\/tools-and-utilities\/nand-system-power-calculator."},{"key":"e_1_3_2_1_39_1","unstructured":"Micron 2018. NAND MLC Flash Memory Datasheet. Micron.  Micron 2018. NAND MLC Flash Memory Datasheet. Micron."},{"key":"e_1_3_2_1_40_1","volume-title":"Data center storage capacity worldwide from 2016 to","author":"Mlitz Kimberly","year":"2021","unstructured":"Kimberly Mlitz . [n.d.]. Data center storage capacity worldwide from 2016 to 2021 . https:\/\/www.statista.com\/statistics\/638593\/worldwide-data-center-storage-capacity-cloud-vs-traditional\/\/. Kimberly Mlitz. [n.d.]. Data center storage capacity worldwide from 2016 to 2021. https:\/\/www.statista.com\/statistics\/638593\/worldwide-data-center-storage-capacity-cloud-vs-traditional\/\/."},{"key":"e_1_3_2_1_41_1","unstructured":"Onur Mutlu Saugata Ghose Juan G\u00f3mez-Luna and Rachata Ausavarungnirun. 2020. A Modern Primer on Processing in Memory. In arXiv preprint arXiv:2012.03112.  Onur Mutlu Saugata Ghose Juan G\u00f3mez-Luna and Rachata Ausavarungnirun. 2020. A Modern Primer on Processing in Memory. In arXiv preprint arXiv:2012.03112."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"crossref","unstructured":"Jisung Park Myungsuk Kim Myoungjun Chun Lois Orosa Jihong Kim and Onur Mutlu. 2020. Reducing Solid State Drive Read Latency by Optimizing Read-Retry. In ASPLOS. ACM.  Jisung Park Myungsuk Kim Myoungjun Chun Lois Orosa Jihong Kim and Onur Mutlu. 2020. Reducing Solid State Drive Read Latency by Optimizing Read-Retry. In ASPLOS. ACM.","DOI":"10.1145\/3445814.3446719"},{"key":"e_1_3_2_1_43_1","volume-title":"INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive. In ATC. USENIX.","author":"Ruan Zhenyuan","year":"2019","unstructured":"Zhenyuan Ruan , Tong He , and Jason Cong . 2019 . INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive. In ATC. USENIX. Zhenyuan Ruan, Tong He, and Jason Cong. 2019. INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive. In ATC. USENIX."},{"key":"e_1_3_2_1_44_1","volume-title":"2015. Imagenet large scale visual recognition challenge","author":"Russakovsky Olga","unstructured":"Olga Russakovsky , Jia Deng , Hao Su , and 2015. Imagenet large scale visual recognition challenge . In IJCV. Springer . Olga Russakovsky, Jia Deng, Hao Su, and et al.2015. Imagenet large scale visual recognition challenge. In IJCV. Springer."},{"key":"e_1_3_2_1_45_1","unstructured":"Arthur Sainio. 2016. NVDIMM: changes are here so what\u2019s next. In Memory Computing Summit.  Arthur Sainio. 2016. NVDIMM: changes are here so what\u2019s next. In Memory Computing Summit."},{"key":"e_1_3_2_1_46_1","unstructured":"Samsung. [n.d.]. Samsung 970 Pro. https:\/\/www.samsung.com\/semiconductor\/minisite\/ssd\/product\/consumer\/970pro\/.  Samsung. [n.d.]. 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Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology","author":"Seshadri Vivek","unstructured":"Vivek Seshadri , Donghyuk Lee , Thomas Mullins , and 2017. Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology . In MICRO. IEEE. Vivek Seshadri, Donghyuk Lee, Thomas Mullins, and et al.2017. Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology. In MICRO. IEEE."},{"key":"e_1_3_2_1_50_1","unstructured":"Yong\u00a0Ho Song Sanghyuk Jung Sang-Won Lee and Jin-Soo Kim. 2014. Cosmos openSSD: A PCIe-based open source SSD platform. In Flash Memory Summit.  Yong\u00a0Ho Song Sanghyuk Jung Sang-Won Lee and Jin-Soo Kim. 2014. Cosmos openSSD: A PCIe-based open source SSD platform. In Flash Memory Summit."},{"key":"e_1_3_2_1_51_1","unstructured":"Synopsys. [n.d.]. H-spice. https:\/\/www.synopsys.com\/.  Synopsys. [n.d.]. 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USENIX."}],"event":{"name":"MICRO '21: 54th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Virtual Event Greece","acronym":"MICRO '21","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480078","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/abs\/10.1145\/3466752.3480078","content-type":"text\/html","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480078","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480078","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:18:56Z","timestamp":1750191536000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480078"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,17]]},"references-count":60,"alternative-id":["10.1145\/3466752.3480078","10.1145\/3466752"],"URL":"https:\/\/doi.org\/10.1145\/3466752.3480078","relation":{},"subject":[],"published":{"date-parts":[[2021,10,17]]},"assertion":[{"value":"2021-10-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}