{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T21:52:07Z","timestamp":1775598727253,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":144,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T00:00:00Z","timestamp":1634428800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,10,18]]},"DOI":"10.1145\/3466752.3480114","type":"proceedings-article","created":{"date-parts":[[2021,10,17]],"date-time":"2021-10-17T19:12:05Z","timestamp":1634497925000},"page":"1121-1137","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":81,"title":["Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning"],"prefix":"10.1145","author":[{"given":"Rahul","family":"Bera","sequence":"first","affiliation":[{"name":"ETH Zurich, Switzerland"}]},{"given":"Konstantinos","family":"Kanellopoulos","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich"}]},{"given":"Anant","family":"Nori","sequence":"additional","affiliation":[{"name":"Intel, India"}]},{"given":"Taha","family":"Shahroodi","sequence":"additional","affiliation":[{"name":"TU Delft, Switzerland"}]},{"given":"Sreenivas","family":"Subramoney","sequence":"additional","affiliation":[{"name":"Intel Labs, India"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Zurich, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2021,10,17]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2nd Cache Replacement Championship. https:\/\/crc2.ece.tamu.edu.  2nd Cache Replacement Championship. https:\/\/crc2.ece.tamu.edu."},{"key":"e_1_3_2_1_2_1","unstructured":"2nd Data Prefetching Championship. http:\/\/comparch-conf.gatech.edu\/dpc2\/.  2nd Data Prefetching Championship. http:\/\/comparch-conf.gatech.edu\/dpc2\/."},{"key":"e_1_3_2_1_3_1","unstructured":"3rd Data Prefetching Championship. https:\/\/dpc3.compas.cs.stonybrook.edu.  3rd Data Prefetching Championship. https:\/\/dpc3.compas.cs.stonybrook.edu."},{"key":"e_1_3_2_1_4_1","unstructured":"6th Generation Intel\u00ae Processor Family. https:\/\/www.intel.com\/content\/www\/us\/en\/processors\/core\/desktop-6th-gen-core-family-spec-update.html.  6th Generation Intel\u00ae Processor Family. https:\/\/www.intel.com\/content\/www\/us\/en\/processors\/core\/desktop-6th-gen-core-family-spec-update.html."},{"key":"e_1_3_2_1_5_1","unstructured":"AMD Ryzen Threadripper 3990X. https:\/\/en.wikichip.org\/wiki\/amd\/ryzen_threadripper\/3990x.  AMD Ryzen Threadripper 3990X. https:\/\/en.wikichip.org\/wiki\/amd\/ryzen_threadripper\/3990x."},{"key":"e_1_3_2_1_6_1","unstructured":"AMD Zen2 EPYC 7702P. https:\/\/en.wikichip.org\/wiki\/amd\/epyc\/7702p.  AMD Zen2 EPYC 7702P. https:\/\/en.wikichip.org\/wiki\/amd\/epyc\/7702p."},{"key":"e_1_3_2_1_7_1","unstructured":"ChampSim. https:\/\/github.com\/ChampSim\/ChampSim.  ChampSim. https:\/\/github.com\/ChampSim\/ChampSim."},{"key":"e_1_3_2_1_8_1","unstructured":"Chisel\/FIRRTL Hardware Compiler Framework. https:\/\/www.chisel-lang.org.  Chisel\/FIRRTL Hardware Compiler Framework. https:\/\/www.chisel-lang.org."},{"key":"e_1_3_2_1_9_1","unstructured":"Disclosure of Hardware Prefetcher Control on Some Intel\u00ae Processors. https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/articles\/disclosure-of-hw-prefetcher-control-on-some-intel-processors.html.  Disclosure of Hardware Prefetcher Control on Some Intel\u00ae Processors. https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/articles\/disclosure-of-hw-prefetcher-control-on-some-intel-processors.html."},{"key":"e_1_3_2_1_10_1","unstructured":"GlobalFoundries 14nm FinFET Technology. https:\/\/www.globalfoundries.com\/sites\/default\/files\/product-briefs\/pb-14lpp.pdf.  GlobalFoundries 14nm FinFET Technology. https:\/\/www.globalfoundries.com\/sites\/default\/files\/product-briefs\/pb-14lpp.pdf."},{"key":"e_1_3_2_1_11_1","unstructured":"Intel Xeon D-2123IT. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_d\/d-2123it.  Intel Xeon D-2123IT. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_d\/d-2123it."},{"key":"e_1_3_2_1_12_1","unstructured":"Intel Xeon Gold 6150. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_gold\/6150.  Intel Xeon Gold 6150. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_gold\/6150."},{"key":"e_1_3_2_1_13_1","unstructured":"Intel Xeon Gold 6258R. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_gold\/6258r.  Intel Xeon Gold 6258R. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_gold\/6258r."},{"key":"e_1_3_2_1_14_1","unstructured":"Intel Xeon Platinum 8180M. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_platinum\/8180m.  Intel Xeon Platinum 8180M. https:\/\/en.wikichip.org\/wiki\/intel\/xeon_platinum\/8180m."},{"key":"e_1_3_2_1_15_1","unstructured":"JEDEC-DDR4. https:\/\/www.jedec.org\/sites\/default\/files\/docs\/JESD79-4.pdf.  JEDEC-DDR4. https:\/\/www.jedec.org\/sites\/default\/files\/docs\/JESD79-4.pdf."},{"key":"e_1_3_2_1_16_1","unstructured":"PARSEC. http:\/\/parsec.cs.princeton.edu\/.  PARSEC. http:\/\/parsec.cs.princeton.edu\/."},{"key":"e_1_3_2_1_17_1","unstructured":"Pin - A Dynamic Binary Instrumentation Tool. https:\/\/software.intel.com\/en-us\/articles\/pin-a-dynamic-binary-instrumentation-tool.  Pin - A Dynamic Binary Instrumentation Tool. https:\/\/software.intel.com\/en-us\/articles\/pin-a-dynamic-binary-instrumentation-tool."},{"key":"e_1_3_2_1_18_1","unstructured":"Pythia. https:\/\/en.wikipedia.org\/wiki\/Pythia.  Pythia. https:\/\/en.wikipedia.org\/wiki\/Pythia."},{"key":"e_1_3_2_1_19_1","unstructured":"Pythia GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/Pythia.  Pythia GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/Pythia."},{"key":"e_1_3_2_1_20_1","unstructured":"Second Championship Value Prediction (CVP-2). https:\/\/www.microarch.org\/cvp1\/cvp2\/rules.html.  Second Championship Value Prediction (CVP-2). https:\/\/www.microarch.org\/cvp1\/cvp2\/rules.html."},{"key":"e_1_3_2_1_21_1","volume-title":"CPU 2006","author":"SPEC","year":"2006","unstructured":"SPEC CPU 2006 . https:\/\/www.spec.org\/cpu 2006 \/. SPEC CPU 2006. https:\/\/www.spec.org\/cpu2006\/."},{"key":"e_1_3_2_1_22_1","volume-title":"CPU 2017","author":"SPEC","year":"2017","unstructured":"SPEC CPU 2017 . https:\/\/www.spec.org\/cpu 2017 \/. SPEC CPU 2017. https:\/\/www.spec.org\/cpu2017\/."},{"key":"e_1_3_2_1_23_1","unstructured":"Synopsys DC Ultra. https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/dc-ultra.html.  Synopsys DC Ultra. https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/dc-ultra.html."},{"key":"e_1_3_2_1_24_1","volume-title":"A New Approach to Manipulator Control: The Cerebellar Model Articulation Controller (CMAC). Journal of Dynamic Systems, Measurement, and Control","author":"Albus S.","year":"1975","unstructured":"J.\u00a0 S. Albus . A New Approach to Manipulator Control: The Cerebellar Model Articulation Controller (CMAC). Journal of Dynamic Systems, Measurement, and Control . 1975 . J.\u00a0S. Albus. A New Approach to Manipulator Control: The Cerebellar Model Articulation Controller (CMAC). Journal of Dynamic Systems, Measurement, and Control. 1975."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00021"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00053"},{"key":"e_1_3_2_1_28_1","volume-title":"Accelerating Deep Learning Inference via Learned Caches","author":"Balasubramanian Arjun","year":"2021","unstructured":"Arjun Balasubramanian , Adarsh Kumar , Yuhan Liu , Han Cao , Shivaram Venkataraman , and Aditya Akella . Accelerating Deep Learning Inference via Learned Caches . 2021 . Arjun Balasubramanian, Adarsh Kumar, Yuhan Liu, Han Cao, Shivaram Venkataraman, and Aditya Akella. Accelerating Deep Learning Inference via Learned Caches. 2021."},{"key":"e_1_3_2_1_29_1","volume-title":"Correlated load-address predictors. ISCA","author":"Bekerman Michael","year":"1999","unstructured":"Michael Bekerman , Stephan Jourdan , Ronny Ronen , Gilad Kirshenboim , Lihu Rappoport , Adi Yoaz , Correlated load-address predictors. ISCA . 1999 . Michael Bekerman, Stephan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Correlated load-address predictors. ISCA. 1999."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358325"},{"key":"e_1_3_2_1_31_1","first-page":"1","volume":"13","unstructured":"James Bergstra and Yoshua Bengio. Random Search for Hyper-parameter Optimization. The Journal of Machine Learning Research 13 , 1 . 2012. James Bergstra and Yoshua Bengio. Random Search for Hyper-parameter Optimization. The Journal of Machine Learning Research 13, 1. 2012.","journal-title":"James Bergstra and Yoshua Bengio. Random Search for Hyper-parameter Optimization. The Journal of Machine Learning Research"},{"key":"e_1_3_2_1_32_1","volume-title":"ISCA.","author":"Bhatia Eshan","year":"2019","unstructured":"Eshan Bhatia , Gino Chacon , Seth Pugsley , Elvira Teran , Paul\u00a0 V. Gratz , and Daniel\u00a0 A. Jim\u00e9nez . Perceptron-Based Prefetch Filtering . In ISCA. 2019 . Eshan Bhatia, Gino Chacon, Seth Pugsley, Elvira Teran, Paul\u00a0V. Gratz, and Daniel\u00a0A. Jim\u00e9nez. Perceptron-Based Prefetch Filtering. In ISCA. 2019."},{"key":"e_1_3_2_1_33_1","volume-title":"ISCA.","author":"Chappell S.","year":"1999","unstructured":"Robert\u00a0 S. Chappell , Jared Stark , Sangwook\u00a0 P. Kim , Steven\u00a0 K. Reinhardt , and Yale\u00a0 N. Patt . Simultaneous Subordinate Microthreading (SSMT) . In ISCA. 1999 . Robert\u00a0S. Chappell, Jared Stark, Sangwook\u00a0P. Kim, Steven\u00a0K. Reinhardt, and Yale\u00a0N. Patt. Simultaneous Subordinate Microthreading (SSMT). In ISCA. 1999."},{"key":"e_1_3_2_1_34_1","volume-title":"Prefetching and Memory System Behavior of the SPEC95 Benchmark Suite. IBM Journal of Research and Development","author":"Charney J.","year":"1997","unstructured":"M.\u00a0 J. Charney and T.\u00a0 R. Puzak . Prefetching and Memory System Behavior of the SPEC95 Benchmark Suite. IBM Journal of Research and Development . 1997 . M.\u00a0J. Charney and T.\u00a0R. Puzak. Prefetching and Memory System Behavior of the SPEC95 Benchmark Suite. IBM Journal of Research and Development. 1997."},{"key":"e_1_3_2_1_35_1","volume-title":"Effective hardware-based data prefetching for high-performance processors","author":"Chen Tien-Fu","year":"1995","unstructured":"Tien-Fu Chen and Jean-Loup Baer . Effective hardware-based data prefetching for high-performance processors . In IEEE TC. 1995 . Tien-Fu Chen and Jean-Loup Baer. Effective hardware-based data prefetching for high-performance processors. In IEEE TC. 1995."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/512529.512554"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.39"},{"key":"e_1_3_2_1_38_1","volume-title":"Proceedings of the Fourteenth International Conference on Artificial Intelligence and Statistics. 208\u2013214","author":"Chu Wei","year":"2011","unstructured":"Wei Chu , Lihong Li , Lev Reyzin , and Robert Schapire . Contextual bandits with linear payoff functions . In Proceedings of the Fourteenth International Conference on Artificial Intelligence and Statistics. 208\u2013214 . 2011 . Wei Chu, Lihong Li, Lev Reyzin, and Robert Schapire. Contextual bandits with linear payoff functions. In Proceedings of the Fourteenth International Conference on Artificial Intelligence and Statistics. 208\u2013214. 2011."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196068"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991128"},{"key":"e_1_3_2_1_41_1","volume-title":"ISCA.","author":"Collins D","year":"2001","unstructured":"Jamison\u00a0 D Collins , Hong Wang , Dean\u00a0 M Tullsen , Christopher Hughes , Yong-Fong Lee , Dan Lavery , Speculative precomputation: Long-range prefetching of delinquent loads . In ISCA. 2001 . Jamison\u00a0D Collins, Hong Wang, Dean\u00a0M Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, Speculative precomputation: Long-range prefetching of delinquent loads. In ISCA. 2001."},{"key":"e_1_3_2_1_42_1","volume-title":"A stateless, content-directed data prefetching mechanism. ASPLOS","author":"Cooksey Robert","year":"2002","unstructured":"Robert Cooksey , Stephan Jourdan , and Dirk Grunwald . A stateless, content-directed data prefetching mechanism. ASPLOS . 2002 . Robert Cooksey, Stephan Jourdan, and Dirk Grunwald. A stateless, content-directed data prefetching mechanism. ASPLOS. 2002."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783734"},{"key":"e_1_3_2_1_44_1","volume-title":"DATE.","author":"DiTomaso Dominic","year":"2017","unstructured":"Dominic DiTomaso , Ashif Sikder , Avinash Kodi , and Ahmed Louri . Machine Learning Enabled Power-aware Network-on-chip Design . In DATE. 2017 . Dominic DiTomaso, Ashif Sikder, Avinash Kodi, and Ahmed Louri. Machine Learning Enabled Power-aware Network-on-chip Design. In DATE. 2017."},{"key":"e_1_3_2_1_46_1","volume-title":"ICS.","author":"Dundas James","year":"1997","unstructured":"James Dundas and Trevor Mudge . Improving Data Cache Performance by Pre-executing Instructions Under a Cache Miss . In ICS. 1997 . James Dundas and Trevor Mudge. Improving Data Cache Performance by Pre-executing Instructions Under a Cache Miss. In ICS. 1997."},{"key":"e_1_3_2_1_47_1","volume-title":"ISCA.","author":"Ebrahimi Eiman","year":"2011","unstructured":"Eiman Ebrahimi , Chang\u00a0Joo Lee , Onur Mutlu , and Yale\u00a0 N. Patt . Prefetch-aware Shared Resource Management for Multi-core Systems . In ISCA. 2011 . Eiman Ebrahimi, Chang\u00a0Joo Lee, Onur Mutlu, and Yale\u00a0N. Patt. Prefetch-aware Shared Resource Management for Multi-core Systems. In ISCA. 2011."},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669154"},{"key":"e_1_3_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798232"},{"key":"e_1_3_2_1_50_1","volume-title":"Maurizio Palesi","author":"Ebrahimi Masoumeh","year":"2012","unstructured":"Masoumeh Ebrahimi , Masoud Daneshtalab , Fahimeh Farahnakian , Juha Plosila , Pasi Liljeberg , Maurizio Palesi , HARAQ : Congestion-aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks. In NOCS. 2012 . Masoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, Juha Plosila, Pasi Liljeberg, Maurizio Palesi, HARAQ: Congestion-aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks. In NOCS. 2012."},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2150982"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2007.363741"},{"key":"e_1_3_2_1_53_1","volume-title":"1st JILP Data Prefetching Championship.","author":"Ferdman Michael","year":"2009","unstructured":"Michael Ferdman , Stephen Somogyi , and Babak Falsafi . Spatial Memory Streaming with Rotated Patterns . In In 1st JILP Data Prefetching Championship. 2009 . Michael Ferdman, Stephen Somogyi, and Babak Falsafi. Spatial Memory Streaming with Rotated Patterns. In In 1st JILP Data Prefetching Championship. 2009."},{"key":"e_1_3_2_1_54_1","volume-title":"Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning techniques","author":"Fettes Quintin","year":"2018","unstructured":"Quintin Fettes , Mark Clark , Razvan Bunescu , Avinash Karanth , and Ahmed Louri . Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning techniques . IEEE TC. 2018 . Quintin Fettes, Mark Clark, Razvan Bunescu, Avinash Karanth, and Ahmed Louri. Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning techniques. IEEE TC. 2018."},{"key":"e_1_3_2_1_55_1","volume-title":"ISCA.","author":"Fu John","year":"1991","unstructured":"John W.\u00a0C. Fu and Janak\u00a0 H. Patel . Data Prefetching in Multiprocessor Vector Cache Memories . In ISCA. 1991 . John W.\u00a0C. Fu and Janak\u00a0H. Patel. Data Prefetching in Multiprocessor Vector Cache Memories. In ISCA. 1991."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697004"},{"key":"e_1_3_2_1_57_1","volume-title":"ISCA.","author":"Garza Elba","year":"2019","unstructured":"Elba Garza , Samira Mirbagher-Ajorpaz , Tahsin\u00a0Ahmad Khan , and Daniel\u00a0 A Jim\u00e9nez . Bit-level Perceptron Prediction for Indirect Branches . In ISCA. 2019 . Elba Garza, Samira Mirbagher-Ajorpaz, Tahsin\u00a0Ahmad Khan, and Daniel\u00a0A Jim\u00e9nez. Bit-level Perceptron Prediction for Indirect Branches. In ISCA. 2019."},{"key":"e_1_3_2_1_58_1","volume-title":"An Introduction to Variable and Feature Selection. Journal of machine learning research","author":"Guyon Isabelle","year":"2003","unstructured":"Isabelle Guyon and Andr\u00e9 Elisseeff . An Introduction to Variable and Feature Selection. Journal of machine learning research 3, Mar. 2003 . Isabelle Guyon and Andr\u00e9 Elisseeff. An Introduction to Variable and Feature Selection. Journal of machine learning research 3, Mar. 2003."},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783764"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830812"},{"key":"e_1_3_2_1_61_1","volume-title":"ICML.","author":"Hashemi Milad","year":"2018","unstructured":"Milad Hashemi , Kevin Swersky , Jamie Smith , Grant Ayers , Heiner Litz , Jichuan Chang , Learning Memory Access Patterns . In ICML. 2018 . Milad Hashemi, Kevin Swersky, Jamie Smith, Grant Ayers, Heiner Litz, Jichuan Chang, Learning Memory Access Patterns. In ICML. 2018."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183549"},{"key":"e_1_3_2_1_63_1","volume-title":"ICS.","author":"Iacobovici Sorin","year":"2004","unstructured":"Sorin Iacobovici , Lawrence Spracklen , Sudarshan Kadambi , Yuan Chou , and Santosh\u00a0 G Abraham . Effective stream-based and execution-based data prefetching . In ICS. 2004 . Sorin Iacobovici, Lawrence Spracklen, Sudarshan Kadambi, Yuan Chou, and Santosh\u00a0G Abraham. Effective stream-based and execution-based data prefetching. In ICS. 2004."},{"key":"e_1_3_2_1_64_1","volume-title":"ISCA.","author":"Ipek E.","year":"2008","unstructured":"E. Ipek , O. Mutlu , J.\u00a0 F. Mart\u00ednez , and R. Caruana . Self-Optimizing Memory Controllers: A Reinforcement Learning Approach . In ISCA. 2008 . E. Ipek, O. Mutlu, J.\u00a0F. Mart\u00ednez, and R. Caruana. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. In ISCA. 2008."},{"key":"e_1_3_2_1_65_1","volume-title":"ISC.","author":"Ishii Yasuo","year":"2009","unstructured":"Yasuo Ishii , Mary Inaba , and Kei Hiraki . Access Map Pattern Matching for Data Cache Prefetch . In ISC. 2009 . Yasuo Ishii, Mary Inaba, and Kei Hiraki. Access Map Pattern Matching for Data Cache Prefetch. In ISC. 2009."},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540730"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253199"},{"key":"e_1_3_2_1_68_1","volume-title":"Jim\u00e9nez. Multiperspective Perceptron Predictor. In 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5).","year":"2016","unstructured":"Daniel\u00a0A Jim\u00e9nez. Multiperspective Perceptron Predictor. In 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5). 2016 . Daniel\u00a0A Jim\u00e9nez. Multiperspective Perceptron Predictor. In 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5). 2016."},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903263"},{"key":"e_1_3_2_1_70_1","volume-title":"Neural methods for dynamic branch prediction. TOCS","author":"Jim\u00e9nez A","year":"2002","unstructured":"Daniel\u00a0 A Jim\u00e9nez and Calvin Lin . Neural methods for dynamic branch prediction. TOCS . 2002 . Daniel\u00a0A Jim\u00e9nez and Calvin Lin. Neural methods for dynamic branch prediction. TOCS. 2002."},{"key":"e_1_3_2_1_71_1","volume-title":"ISCA.","author":"Joseph Doug","year":"1997","unstructured":"Doug Joseph and Dirk Grunwald . Prefetching using Markov predictors . In ISCA. 1997 . Doug Joseph and Dirk Grunwald. Prefetching using Markov predictors. In ISCA. 1997."},{"key":"e_1_3_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/325164.325162"},{"key":"e_1_3_2_1_73_1","volume-title":"IPDPS.","author":"Jung Changhee","year":"2006","unstructured":"Changhee Jung , Daeseob Lim , Jaejin Lee , and Y. Solihin . Helper thread prefetching for loosely-coupled multiprocessor systems . In IPDPS. 2006 . Changhee Jung, Daeseob Lim, Jaejin Lee, and Y. Solihin. Helper thread prefetching for loosely-coupled multiprocessor systems. In IPDPS. 2006."},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.29"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00058"},{"key":"e_1_3_2_1_76_1","volume-title":"HPCA).","author":"Karlsson Magnus","year":"2000","unstructured":"Magnus Karlsson , Fredrik Dahlgren , and Per Stenstrom . A prefetching technique for irregular accesses to linked data structures . In HPCA). 2000 . Magnus Karlsson, Fredrik Dahlgren, and Per Stenstrom. A prefetching technique for irregular accesses to linked data structures. In HPCA). 2000."},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783763"},{"key":"e_1_3_2_1_78_1","volume-title":"ISCA.","author":"Kondguli Sushant","year":"2018","unstructured":"Sushant Kondguli and Michael Huang . Division of labor: A more effective approach to prefetching . In ISCA. 2018 . Sushant Kondguli and Michael Huang. Division of labor: A more effective approach to prefetching. In ISCA. 2018."},{"key":"e_1_3_2_1_79_1","volume-title":"ISCA.","author":"Kumar Sanjeev","year":"1998","unstructured":"Sanjeev Kumar and Christopher Wilkerson . Exploiting Spatial Locality in Data Caches using Spatial Footprints . In ISCA. 1998 . Sanjeev Kumar and Christopher Wilkerson. Exploiting Spatial Locality in Data Caches using Spatial Footprints. In ISCA. 1998."},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771791"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669155"},{"key":"e_1_3_2_1_82_1","volume-title":"Fitting Segmented Regression Models by Grid Search. Journal of the Royal Statistical Society: Series C (Applied Statistics) 29, 1","author":"Lerman PM","year":"1980","unstructured":"PM Lerman . Fitting Segmented Regression Models by Grid Search. Journal of the Royal Statistical Society: Series C (Applied Statistics) 29, 1 . 1980 . PM Lerman. Fitting Segmented Regression Models by Grid Search. Journal of the Royal Statistical Society: Series C (Applied Statistics) 29, 1. 1980."},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00018"},{"key":"e_1_3_2_1_84_1","volume-title":"HPCA.","author":"Lin Wei-Fen","year":"2001","unstructured":"Wei-Fen Lin , S.K. Reinhardt , and D. Burger . Reducing DRAM Latencies with an Integrated Memory Hierarchy Design . In HPCA. 2001 . Wei-Fen Lin, S.K. Reinhardt, and D. Burger. Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. In HPCA. 2001."},{"key":"e_1_3_2_1_85_1","volume-title":"ICCD.","author":"Lin Wei-Fen","year":"2001","unstructured":"Wei-Fen Lin , S.K. Reinhardt , D. Burger , and T.R. Puzak . Filtering superfluous prefetches using density vectors . In ICCD. 2001 . Wei-Fen Lin, S.K. Reinhardt, D. Burger, and T.R. Puzak. Filtering superfluous prefetches using density vectors. In ICCD. 2001."},{"key":"e_1_3_2_1_86_1","volume-title":"ICML.","author":"Liu Evan","year":"2020","unstructured":"Evan Liu , Milad Hashemi , Kevin Swersky , Parthasarathy Ranganathan , and Junwhan Ahn . An imitation learning approach for cache replacement . In ICML. 2020 . Evan Liu, Milad Hashemi, Kevin Swersky, Parthasarathy Ranganathan, and Junwhan Ahn. An imitation learning approach for cache replacement. In ICML. 2020."},{"key":"e_1_3_2_1_87_1","volume-title":"ISCA.","author":"Luk Chi-Keung","year":"2001","unstructured":"Chi-Keung Luk . Tolerating Memory Latency Through Software-controlled Pre-execution in Simultaneous Multithreading Processors . In ISCA. 2001 . Chi-Keung Luk. Tolerating Memory Latency Through Software-controlled Pre-execution in Simultaneous Multithreading Processors. In ISCA. 2001."},{"key":"e_1_3_2_1_88_1","volume-title":"ML for Systems at NeurIPS.","author":"Margaritov Artemiy","year":"2018","unstructured":"Artemiy Margaritov , Dmitrii Ustiugov , Edouard Bugnion , and Boris Grot . Virtual address translation via learned page table indexes . In ML for Systems at NeurIPS. 2018 . Artemiy Margaritov, Dmitrii Ustiugov, Edouard Bugnion, and Boris Grot. Virtual address translation via learned page table indexes. In ML for Systems at NeurIPS. 2018."},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446087"},{"key":"e_1_3_2_1_90_1","volume-title":"A Graph Placement Methodology for Fast Chip Design. Nature","author":"Mirhoseini Azalia","year":"2021","unstructured":"Azalia Mirhoseini , Anna Goldie , Mustafa Yazgan , Joe\u00a0Wenjie Jiang , Ebrahim Songhori , Shen Wang , A Graph Placement Methodology for Fast Chip Design. Nature . 2021 . Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe\u00a0Wenjie Jiang, Ebrahim Songhori, Shen Wang, A Graph Placement Methodology for Fast Chip Design. Nature. 2021."},{"key":"e_1_3_2_1_91_1","volume-title":"Human-level control through deep reinforcement learning. Nature","author":"Mnih Volodymyr","year":"2015","unstructured":"Volodymyr Mnih , Koray Kavukcuoglu , David Silver , Andrei\u00a0 A Rusu , Joel Veness , Marc\u00a0 G Bellemare , Human-level control through deep reinforcement learning. Nature . 2015 . Volodymyr Mnih, Koray Kavukcuoglu, David Silver, Andrei\u00a0A Rusu, Joel Veness, Marc\u00a0G Bellemare, Human-level control through deep reinforcement learning. Nature. 2015."},{"key":"e_1_3_2_1_92_1","volume-title":"Introduction to linear regression analysis. Vol.\u00a0821","author":"Montgomery C","year":"2012","unstructured":"Douglas\u00a0 C Montgomery , Elizabeth\u00a0 A Peck , and G\u00a0Geoffrey Vining . Introduction to linear regression analysis. Vol.\u00a0821 . John Wiley & Sons . 2012 . Douglas\u00a0C Montgomery, Elizabeth\u00a0A Peck, and G\u00a0Geoffrey Vining. Introduction to linear regression analysis. Vol.\u00a0821. John Wiley & Sons. 2012."},{"key":"e_1_3_2_1_93_1","volume-title":"ISCA.","author":"Mukundan Janani","year":"2012","unstructured":"Janani Mukundan and Jose\u00a0 F Martinez . MORSE: Multi-objective Reconfigurable Self-optimizing Memory Scheduler . In ISCA. 2012 . Janani Mukundan and Jose\u00a0F Martinez. MORSE: Multi-objective Reconfigurable Self-optimizing Memory Scheduler. In ISCA. 2012."},{"key":"e_1_3_2_1_94_1","volume-title":"Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. IJPP","author":"Mutlu Onur","year":"2005","unstructured":"Onur Mutlu , Hyesoon Kim , David\u00a0 N Armstrong , and Yale\u00a0 N Patt . Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. IJPP . 2005 . Onur Mutlu, Hyesoon Kim, David\u00a0N Armstrong, and Yale\u00a0N Patt. Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. IJPP. 2005."},{"key":"e_1_3_2_1_95_1","volume-title":"MICRO.","author":"Mutlu Onur","year":"2005","unstructured":"Onur Mutlu , Hyesoon Kim , and Yale\u00a0 N Patt . Address-value Delta (AVD) prediction : Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns . In MICRO. 2005 . Onur Mutlu, Hyesoon Kim, and Yale\u00a0N Patt. Address-value Delta (AVD) prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. In MICRO. 2005."},{"key":"e_1_3_2_1_96_1","volume-title":"ISCA.","author":"Mutlu Onur","year":"2005","unstructured":"Onur Mutlu , Hyesoon Kim , and Yale\u00a0 N Patt . Techniques for Efficient Processing in Runahead Execution Engines . In ISCA. 2005 . Onur Mutlu, Hyesoon Kim, and Yale\u00a0N Patt. Techniques for Efficient Processing in Runahead Execution Engines. In ISCA. 2005."},{"key":"e_1_3_2_1_97_1","volume-title":"Efficient Runahead Execution: Power-efficient Memory Latency Tolerance","author":"Mutlu Onur","year":"2006","unstructured":"Onur Mutlu , Hyesoon Kim , and Yale\u00a0 N Patt . Efficient Runahead Execution: Power-efficient Memory Latency Tolerance . In IEEE Micro . 2006 . Onur Mutlu, Hyesoon Kim, and Yale\u00a0N Patt. Efficient Runahead Execution: Power-efficient Memory Latency Tolerance. In IEEE Micro. 2006."},{"key":"e_1_3_2_1_98_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2005.1"},{"key":"e_1_3_2_1_99_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2003.1183532"},{"key":"e_1_3_2_1_100_1","volume-title":"Runahead Execution: An Effective Alternative to Large Instruction Windows","author":"Mutlu Onur","year":"2003","unstructured":"Onur Mutlu , Jared Stark , Chris Wilkerson , and Yale\u00a0 N. Patt . Runahead Execution: An Effective Alternative to Large Instruction Windows . In IEEE Micro . 2003 . Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale\u00a0N. Patt. Runahead Execution: An Effective Alternative to Large Instruction Windows. In IEEE Micro. 2003."},{"key":"e_1_3_2_1_101_1","volume-title":"ISCA.","author":"Naithani Ajeya","year":"2021","unstructured":"Ajeya Naithani , Sam Ainsworth , Timothy\u00a0 M. Jones , and Lieven Eeckhout . Vector Runahead . In ISCA. 2021 . Ajeya Naithani, Sam Ainsworth, Timothy\u00a0M. Jones, and Lieven Eeckhout. Vector Runahead. In ISCA. 2021."},{"key":"e_1_3_2_1_102_1","volume-title":"ISCA.","author":"Pakalapati S.","year":"2020","unstructured":"S. Pakalapati and B. Panda . Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching . In ISCA. 2020 . S. Pakalapati and B. Panda. Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching. In ISCA. 2020."},{"key":"e_1_3_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749473"},{"key":"e_1_3_2_1_104_1","volume-title":"A neural network memory prefetcher using semantic locality. arXiv preprint arXiv:1804.00478","author":"Peled Leeor","year":"2018","unstructured":"Leeor Peled , Uri Weiser , and Yoav Etsion . A neural network memory prefetcher using semantic locality. arXiv preprint arXiv:1804.00478 . 2018 . Leeor Peled, Uri Weiser, and Yoav Etsion. A neural network memory prefetcher using semantic locality. arXiv preprint arXiv:1804.00478. 2018."},{"key":"e_1_3_2_1_105_1","volume-title":"Aamer Jaleel","author":"Pugsley H","year":"2014","unstructured":"Seth\u00a0 H Pugsley , Zeshan Chishti , Chris Wilkerson , Peng-fei Chuang, Robert\u00a0 L Scott , Aamer Jaleel , Sandbox Prefetching : Safe Run-time Evaluation of Aggressive Prefetchers. In HPCA. 2014 . Seth\u00a0H Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert\u00a0L Scott, Aamer Jaleel, Sandbox Prefetching: Safe Run-time Evaluation of Aggressive Prefetchers. In HPCA. 2014."},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658635"},{"key":"e_1_3_2_1_107_1","volume-title":"On-line Q-learning using connectionist systems","author":"Rummery A","year":"1994","unstructured":"Gavin\u00a0 A Rummery and Mahesan Niranjan . On-line Q-learning using connectionist systems . University of Cambridge , Department of Engineering Cambridge, UK. 1994 . Gavin\u00a0A Rummery and Mahesan Niranjan. On-line Q-learning using connectionist systems. University of Cambridge, Department of Engineering Cambridge, UK. 1994."},{"key":"e_1_3_2_1_108_1","volume-title":"Linear regression analysis. Vol.\u00a0329","author":"Seber AF","year":"2012","unstructured":"George\u00a0 AF Seber and Alan\u00a0 J Lee . Linear regression analysis. Vol.\u00a0329 . John Wiley & Sons . 2012 . George\u00a0AF Seber and Alan\u00a0J Lee. Linear regression analysis. Vol.\u00a0329. John Wiley & Sons. 2012."},{"key":"e_1_3_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00033"},{"key":"e_1_3_2_1_110_1","volume-title":"Multi-lookahead offset prefetching","author":"Shakerinava Mehran","year":"2019","unstructured":"Mehran Shakerinava , Mohammad Bakhshalipour , Pejman Lotfi-Kamran , and Hamid Sarbazi-Azad . Multi-lookahead offset prefetching . 2019 . Mehran Shakerinava, Mohammad Bakhshalipour, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad. Multi-lookahead offset prefetching. 2019."},{"key":"e_1_3_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830793"},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358319"},{"key":"e_1_3_2_1_113_1","volume-title":"Calvin Lin. A Neural Hierarchical Sequence Model for Irregular Data Prefetching. In ML For Systems Workshop, NeurIPS.","author":"Shi Zhan","year":"2019","unstructured":"Zhan Shi , Akanksha Jain , Kevin Swersky , Milad Hashemi , Parthasarathy Ranganathan , and Calvin Lin. A Neural Hierarchical Sequence Model for Irregular Data Prefetching. In ML For Systems Workshop, NeurIPS. 2019 . Zhan Shi, Akanksha Jain, Kevin Swersky, Milad Hashemi, Parthasarathy Ranganathan, and Calvin Lin. A Neural Hierarchical Sequence Model for Irregular Data Prefetching. In ML For Systems Workshop, NeurIPS. 2019."},{"key":"e_1_3_2_1_114_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446752"},{"key":"e_1_3_2_1_115_1","volume-title":"Learning execution through neural code fusion. arXiv preprint arXiv:1906.07181","author":"Shi Zhan","year":"2019","unstructured":"Zhan Shi , Kevin Swersky , Daniel Tarlow , Parthasarathy Ranganathan , and Milad Hashemi . Learning execution through neural code fusion. arXiv preprint arXiv:1906.07181 . 2019 . Zhan Shi, Kevin Swersky, Daniel Tarlow, Parthasarathy Ranganathan, and Milad Hashemi. Learning execution through neural code fusion. arXiv preprint arXiv:1906.07181. 2019."},{"key":"e_1_3_2_1_116_1","volume-title":"Shun and Guy\u00a0E Blelloch. Ligra: A Lightweight Graph Processing Framework for Shared Memory. In Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming. 135\u2013146","author":"Julian","year":"2013","unstructured":"Julian Shun and Guy\u00a0E Blelloch. Ligra: A Lightweight Graph Processing Framework for Shared Memory. In Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming. 135\u2013146 . 2013 . Julian Shun and Guy\u00a0E Blelloch. Ligra: A Lightweight Graph Processing Framework for Shared Memory. In Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming. 135\u2013146. 2013."},{"key":"e_1_3_2_1_117_1","volume-title":"Mastering the game of Go with deep neural networks and tree search. Nature.","author":"Silver David","year":"2016","unstructured":"David Silver , Aja Huang , Chris\u00a0 J Maddison , Arthur Guez , Laurent Sifre , George Van Den\u00a0Driessche , Mastering the game of Go with deep neural networks and tree search. Nature. 2016 . David Silver, Aja Huang, Chris\u00a0J Maddison, Arthur Guez, Laurent Sifre, George Van Den\u00a0Driessche, Mastering the game of Go with deep neural networks and tree search. Nature. 2016."},{"key":"e_1_3_2_1_118_1","volume-title":"A general reinforcement learning algorithm that masters chess, shogi, and Go through self-play. Science","author":"Silver David","year":"2018","unstructured":"David Silver , Thomas Hubert , Julian Schrittwieser , Ioannis Antonoglou , Matthew Lai , Arthur Guez , A general reinforcement learning algorithm that masters chess, shogi, and Go through self-play. Science . 2018 . David Silver, Thomas Hubert, Julian Schrittwieser, Ioannis Antonoglou, Matthew Lai, Arthur Guez, A general reinforcement learning algorithm that masters chess, shogi, and Go through self-play. Science. 2018."},{"key":"e_1_3_2_1_119_1","volume-title":"ISCA.","author":"Solihin Yan","year":"2002","unstructured":"Yan Solihin , Jaejin Lee , and Josep Torrellas . Using a user-level memory thread for correlation prefetching . In ISCA. 2002 . Yan Solihin, Jaejin Lee, and Josep Torrellas. Using a user-level memory thread for correlation prefetching. In ISCA. 2002."},{"key":"e_1_3_2_1_120_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555766"},{"key":"e_1_3_2_1_121_1","volume-title":"ISCA.","author":"Somogyi Stephen","year":"2006","unstructured":"Stephen Somogyi , Thomas\u00a0 F Wenisch , Anastassia Ailamaki , Babak Falsafi , and Andreas Moshovos . Spatial Memory Streaming . In ISCA. 2006 . Stephen Somogyi, Thomas\u00a0F Wenisch, Anastassia Ailamaki, Babak Falsafi, and Andreas Moshovos. Spatial Memory Streaming. In ISCA. 2006."},{"key":"e_1_3_2_1_122_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346185"},{"key":"e_1_3_2_1_123_1","volume-title":"Reinforcement Learning: An Introduction","author":"Sutton S.","year":"2017","unstructured":"Richard\u00a0 S. Sutton and Andrew\u00a0 G. Barto . Reinforcement Learning: An Introduction . In MIT Press . 2017 . Richard\u00a0S. Sutton and Andrew\u00a0G. Barto. Reinforcement Learning: An Introduction. In MIT Press. 2017."},{"key":"e_1_3_2_1_124_1","volume-title":"Merging path and gshare indexing in perceptron branch prediction. TACO","author":"Tarjan David","year":"2005","unstructured":"David Tarjan and Kevin Skadron . Merging path and gshare indexing in perceptron branch prediction. TACO . 2005 . David Tarjan and Kevin Skadron. Merging path and gshare indexing in perceptron branch prediction. TACO. 2005."},{"key":"e_1_3_2_1_125_1","volume-title":"Improving branch prediction by modeling global history with convolutional neural networks. arXiv preprint arXiv:1906.09889","author":"Tarsa J","year":"2019","unstructured":"Stephen\u00a0 J Tarsa , Chit-Kwan Lin , Gokce Keskin , Gautham Chinya , and Hong Wang . Improving branch prediction by modeling global history with convolutional neural networks. arXiv preprint arXiv:1906.09889 . 2019 . Stephen\u00a0J Tarsa, Chit-Kwan Lin, Gokce Keskin, Gautham Chinya, and Hong Wang. Improving branch prediction by modeling global history with convolutional neural networks. arXiv preprint arXiv:1906.09889. 2019."},{"key":"e_1_3_2_1_126_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783705"},{"key":"e_1_3_2_1_127_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00048"},{"key":"e_1_3_2_1_128_1","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024411"},{"key":"e_1_3_2_1_129_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798239"},{"key":"e_1_3_2_1_130_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.21"},{"key":"e_1_3_2_1_131_1","volume-title":"ISCA.","author":"Wenisch F","year":"2005","unstructured":"Thomas\u00a0 F Wenisch , Stephen Somogyi , Nikolaos Hardavellas , Jangwoo Kim , Anastassia Ailamaki , and Babak Falsafi . Temporal streaming of shared memory . In ISCA. 2005 . Thomas\u00a0F Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, and Babak Falsafi. Temporal streaming of shared memory. In ISCA. 2005."},{"key":"e_1_3_2_1_132_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"e_1_3_2_1_133_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358300"},{"key":"e_1_3_2_1_134_1","volume-title":"ISCA.","author":"Wu H.","year":"2019","unstructured":"H. Wu , K. Nathella , D. Sunwoo , A. Jain , and C. Lin . Efficient Metadata Management for Irregular Data Prefetching . In ISCA. 2019 . H. Wu, K. Nathella, D. Sunwoo, A. Jain, and C. Lin. Efficient Metadata Management for Irregular Data Prefetching. In ISCA. 2019."},{"key":"e_1_3_2_1_135_1","volume-title":"AIDArc.","author":"Yin Jieming","year":"2018","unstructured":"Jieming Yin , Yasuko Eckert , Shuai Che , Mark Oskin , and Gabriel\u00a0 H Loh . Toward More Efficient NoC Arbitration: A Deep Reinforcement Learning Approach . In AIDArc. 2018 . Jieming Yin, Yasuko Eckert, Shuai Che, Mark Oskin, and Gabriel\u00a0H Loh. Toward More Efficient NoC Arbitration: A Deep Reinforcement Learning Approach. In AIDArc. 2018."},{"key":"e_1_3_2_1_136_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00058"},{"key":"e_1_3_2_1_137_1","volume-title":"Mark Grondona. Slurm: Simple Linux Utility for Resource Management. In Workshop on job scheduling strategies for parallel processing. Springer, 44\u201360","author":"Yoo B","year":"2003","unstructured":"Andy\u00a0 B Yoo , Morris\u00a0 A Jette , and Mark Grondona. Slurm: Simple Linux Utility for Resource Management. In Workshop on job scheduling strategies for parallel processing. Springer, 44\u201360 . 2003 . Andy\u00a0B Yoo, Morris\u00a0A Jette, and Mark Grondona. Slurm: Simple Linux Utility for Resource Management. In Workshop on job scheduling strategies for parallel processing. Springer, 44\u201360. 2003."},{"key":"e_1_3_2_1_138_1","volume-title":"MICRO.","author":"Zangeneh Siavash","year":"2020","unstructured":"Siavash Zangeneh , Stephen Pruett , Sangkug Lym , and Yale Patt . BranchNet : Using Offline Deep Learning To Predict Hard-To-Predict Branches . In MICRO. 2020 . Siavash Zangeneh, Stephen Pruett, Sangkug Lym, and Yale Patt. BranchNet : Using Offline Deep Learning To Predict Hard-To-Predict Branches. In MICRO. 2020."},{"key":"e_1_3_2_1_139_1","volume-title":"Branch prediction with multilayer neural networks: The value of specialization. Machine Learning for Computer Architecture and Systems","author":"Zangeneh Siavash","year":"2020","unstructured":"Siavash Zangeneh , Stephen Pruett , and Yale Patt . Branch prediction with multilayer neural networks: The value of specialization. Machine Learning for Computer Architecture and Systems . 2020 . Siavash Zangeneh, Stephen Pruett, and Yale Patt. Branch prediction with multilayer neural networks: The value of specialization. Machine Learning for Computer Architecture and Systems. 2020."},{"key":"e_1_3_2_1_140_1","doi-asserted-by":"publisher","DOI":"10.1145\/3132402.3132405"},{"key":"e_1_3_2_1_141_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346187"},{"key":"e_1_3_2_1_142_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317768"},{"key":"e_1_3_2_1_143_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2003.1240591"},{"key":"e_1_3_2_1_144_1","volume-title":"ISCA.","author":"Zilles Craig","year":"2001","unstructured":"Craig Zilles and Gurindar Sohi . Execution-based Prediction Using Speculative Slices . In ISCA. 2001 . Craig Zilles and Gurindar Sohi. Execution-based Prediction Using Speculative Slices. In ISCA. 2001."},{"key":"e_1_3_2_1_145_1","volume-title":"Branch Prediction as a Reinforcement Learning Problem: Why, How and Case Studies. ArXiv abs\/2106.13429","author":"Zouzias Anastasios","year":"2021","unstructured":"Anastasios Zouzias , Kleovoulos Kalaitzidis , and Boris Grot . Branch Prediction as a Reinforcement Learning Problem: Why, How and Case Studies. ArXiv abs\/2106.13429 . 2021 . Anastasios Zouzias, Kleovoulos Kalaitzidis, and Boris Grot. Branch Prediction as a Reinforcement Learning Problem: Why, How and Case Studies. ArXiv abs\/2106.13429. 2021."}],"event":{"name":"MICRO '21: 54th Annual IEEE\/ACM International Symposium on Microarchitecture","location":"Virtual Event Greece","acronym":"MICRO '21","sponsor":["SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing"]},"container-title":["MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480114","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3466752.3480114","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:18:57Z","timestamp":1750191537000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3466752.3480114"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10,17]]},"references-count":144,"alternative-id":["10.1145\/3466752.3480114","10.1145\/3466752"],"URL":"https:\/\/doi.org\/10.1145\/3466752.3480114","relation":{},"subject":[],"published":{"date-parts":[[2021,10,17]]},"assertion":[{"value":"2021-10-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}