{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:22:23Z","timestamp":1750220543014,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,6,21]],"date-time":"2021-06-21T00:00:00Z","timestamp":1624233600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,6,21]]},"DOI":"10.1145\/3468044.3468048","type":"proceedings-article","created":{"date-parts":[[2021,6,21]],"date-time":"2021-06-21T10:43:03Z","timestamp":1624272183000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Automation of Domain-specific FPGA-IP Generation and Test"],"prefix":"10.1145","author":[{"given":"Yuya","family":"Nakazato","sequence":"first","affiliation":[{"name":"Kumamoto University"}]},{"given":"Motoki","family":"Amagasaki","sequence":"additional","affiliation":[{"name":"Kumamoto University"}]},{"given":"Qian","family":"Zhao","sequence":"additional","affiliation":[{"name":"Kyushu Institute of Technology"}]},{"given":"Masahiro","family":"Iida","sequence":"additional","affiliation":[{"name":"Kumamoto University"}]},{"given":"Morihiro","family":"Kuga","sequence":"additional","affiliation":[{"name":"Kumamoto University"}]}],"member":"320","published-online":{"date-parts":[[2021,6,21]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"12","article-title":"SLM: A Scalable Logic Module Architecture with Less Configuration Memory","volume":"99","author":"Amagasaki M.","year":"2016","journal-title":"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1145\/3431920.3439297"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.1145\/3431920.3439302"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1145\/3431920.3439294"},{"unstructured":"Xilinx \"Zynq-7000 SoC Datasheet: Abstruct \" https:\/\/japan.xilinx.com\/support\/documentation\/data_sheets\/j_ds190-Zynq-7000-Overview.pdf  Xilinx \"Zynq-7000 SoC Datasheet: Abstruct \" https:\/\/japan.xilinx.com\/support\/documentation\/data_sheets\/j_ds190-Zynq-7000-Overview.pdf","key":"e_1_3_2_1_5_1"},{"unstructured":"Achronix. 2020. Speedcore eFPGA. (2020).  Achronix. 2020. Speedcore eFPGA. (2020).","key":"e_1_3_2_1_6_1"},{"unstructured":"QuickLogic. 2020. ArcticPro. (2020).  QuickLogic. 2020. ArcticPro. (2020).","key":"e_1_3_2_1_7_1"},{"unstructured":"FlexLogix. 2020. EFLX\u00ae. (2020).  FlexLogix. 2020. EFLX\u00ae. (2020).","key":"e_1_3_2_1_8_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1145\/2145694.2145708"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_10_1","DOI":"10.1145\/3024063"},{"unstructured":"V. Bets \"175.vpr SPEC CPU2000 Benchmark Description File \" http:\/\/www.spec.org\/osg\/cpu2000\/CINT2000\/175.vpr\/docs\/175.vpr.html  V. Bets \"175.vpr SPEC CPU2000 Benchmark Description File \" http:\/\/www.spec.org\/osg\/cpu2000\/CINT2000\/175.vpr\/docs\/175.vpr.html","key":"e_1_3_2_1_11_1"},{"key":"e_1_3_2_1_12_1","first-page":"2","article-title":"An easily testable routing architecture and prototype chip","volume":"95","author":"Inoue K.","year":"2012","journal-title":"IEICE TRANS. INF. & SYST."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.5555\/647929.740070"},{"key":"e_1_3_2_1_14_1","first-page":"4","article-title":"Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core","volume":"100","author":"Amagasaki M.","year":"2017","journal-title":"IEICE Transactions on Information and Systems"},{"key":"e_1_3_2_1_15_1","first-page":"8","article-title":"FPGA Design Framework Combined with Commercial VLSI CAD","volume":"96","author":"Zhao Q.","year":"2013","journal-title":"IEICE TRANS. INF. & SYST."},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_16_1","DOI":"10.1007\/11681878_14"}],"event":{"sponsor":["German Research Foundation German Research Foundation"],"acronym":"HEART '21","name":"HEART '21: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","location":"Online Germany"},"container-title":["Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3468044.3468048","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3468044.3468048","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:06Z","timestamp":1750195686000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3468044.3468048"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,21]]},"references-count":16,"alternative-id":["10.1145\/3468044.3468048","10.1145\/3468044"],"URL":"https:\/\/doi.org\/10.1145\/3468044.3468048","relation":{},"subject":[],"published":{"date-parts":[[2021,6,21]]},"assertion":[{"value":"2021-06-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}