{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:22:22Z","timestamp":1750220542737,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,6,21]],"date-time":"2021-06-21T00:00:00Z","timestamp":1624233600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"JST, CREST, Japan","award":["JPMJCR19K1"],"award-info":[{"award-number":["JPMJCR19K1"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,6,21]]},"DOI":"10.1145\/3468044.3468049","type":"proceedings-article","created":{"date-parts":[[2021,6,21]],"date-time":"2021-06-21T10:43:03Z","timestamp":1624272183000},"page":"1-6","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["A programming environment for multi-FPGA systems based on CyberWorkBench"],"prefix":"10.1145","author":[{"given":"Hiroaki","family":"Suzuki","sequence":"first","affiliation":[{"name":"Keio University, Hiyoshi, Yokohama, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wataru","family":"Takahashi","sequence":"additional","affiliation":[{"name":"NEC Corporation, Shiba, Minato-ku, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazutoshi","family":"Wakabayashi","sequence":"additional","affiliation":[{"name":"The University of Tokyo, Hongo, Bunkyo-ku, Tokyo, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hideharu","family":"Amano","sequence":"additional","affiliation":[{"name":"Keio University, Hiyoshi, Yokohama, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,6,21]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ETSI. In https:\/\/www.etsi.org\/technologies\/multi-access-edge-computing.  ETSI. In https:\/\/www.etsi.org\/technologies\/multi-access-edge-computing."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-78890-6_4"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/PDCAT.2017.00052"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2019.00053"},{"key":"e_1_3_2_1_5_1","unstructured":"PALTEK. In paltek.co.jp\/design\/original\/m-kubos\/index.html.  PALTEK. In paltek.co.jp\/design\/original\/m-kubos\/index.html."},{"key":"e_1_3_2_1_6_1","volume-title":"IEEE HotChips 2009","author":"Chow A. Patal","year":"2009","unstructured":"A. Patal C.Madill P. Chow , M. Saladana . Programming the nallatech xeon+multifpga heterogeneous platform . In IEEE HotChips 2009 , Aug. 2009 . A. Patal C.Madill P.Chow, M.Saladana. Programming the nallatech xeon+multifpga heterogeneous platform. In IEEE HotChips 2009, Aug. 2009."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293909"},{"key":"e_1_3_2_1_8_1","volume-title":"FPL2017","author":"Greaves D. J.","year":"2017","unstructured":"D. J. Greaves . Kiwi scientific accleration at large incremental compilation and multi-fpga hls . In FPL2017 , Sept. 2017 . D. J. Greaves. Kiwi scientific accleration at large incremental compilation and multi-fpga hls. In FPL2017, Sept. 2017."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC-SmartCity-DSS.2016.0115"},{"key":"e_1_3_2_1_10_1","volume-title":"CANDAR2020 Workshop SUSCW","author":"Yamauchi Yugo","year":"2020","unstructured":"Yugo Yamauchi , Akram Ben Ahmed , Kazuei Hironaka , Kensuke Iizuka , and Hideharu Amano . Horizontal division of deep learning applications with all-to-all communication on a multi-fpga system . In CANDAR2020 Workshop SUSCW , 2020 . Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, and Hideharu Amano. Horizontal division of deep learning applications with all-to-all communication on a multi-fpga system. In CANDAR2020 Workshop SUSCW, 2020."},{"key":"e_1_3_2_1_11_1","first-page":"12","volume":"103","author":"Sun Yuxi","year":"2020","unstructured":"Yuxi Sun and Hideharu Amano . Fic-rnn: A multi-fpga acceleration framework for deep recurrent neural networks. In IEICE Trans. on Inf&Tech , Vol. E103 -D, No. 12 , Dec. 2020 , Dec. 2020. Yuxi Sun and Hideharu Amano. Fic-rnn: A multi-fpga acceleration framework for deep recurrent neural networks. In IEICE Trans. on Inf&Tech, Vol. E103-D, No. 12, Dec. 2020, Dec. 2020.","journal-title":"Trans. on Inf&Tech"},{"key":"e_1_3_2_1_12_1","volume-title":"16th International Symposium on Applied Reconfigurable Computing","author":"Imdad Ullah M. M.","year":"2020","unstructured":"M. M. Imdad Ullah , Akram Ben Ahmed , and Hideharu Amano . Implementation of fm-index based pattern search on a multi-fpga system . In 16th International Symposium on Applied Reconfigurable Computing , Nov. 2020 . M. M. Imdad Ullah, Akram Ben Ahmed, and Hideharu Amano. Implementation of fm-index based pattern search on a multi-fpga system. In 16th International Symposium on Applied Reconfigurable Computing, Nov. 2020."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/CANDARW51189.2020.00049"},{"key":"e_1_3_2_1_14_1","volume-title":"System design with systemc","author":"Groetker G.","year":"2010","unstructured":"G. Martin S.Swan T. Groetker , S. Liao . System design with systemc . In Kluwer Academic Publishers , 2010 . G.Martin S.Swan T.Groetker, S.Liao. System design with systemc. In Kluwer Academic Publishers, 2010."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"}],"event":{"name":"HEART '21: International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","sponsor":["German Research Foundation German Research Foundation"],"location":"Online Germany","acronym":"HEART '21"},"container-title":["Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3468044.3468049","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3468044.3468049","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T21:28:06Z","timestamp":1750195686000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3468044.3468049"}},"subtitle":["an integrated design tool"],"short-title":[],"issued":{"date-parts":[[2021,6,21]]},"references-count":15,"alternative-id":["10.1145\/3468044.3468049","10.1145\/3468044"],"URL":"https:\/\/doi.org\/10.1145\/3468044.3468049","relation":{},"subject":[],"published":{"date-parts":[[2021,6,21]]},"assertion":[{"value":"2021-06-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}