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Archit. Code Optim."],"published-print":{"date-parts":[[2021,12,31]]},"abstract":"<jats:p>\n            Despite being employed in numerous efforts to improve power delivery efficiency, the integrated voltage regulator (IVR) approach has yet to be evaluated rigorously and quantitatively in a full power delivery system (PDS) setting. To fulfill this need, we present a system-level modeling and design space exploration framework called\n            <jats:italic>Ivory<\/jats:italic>\n            for IVR-assisted power delivery systems. Using a novel modeling methodology, it can accurately estimate power delivery efficiency, static performance characteristics, and dynamic transient responses under different load variations and external voltage\/frequency scaling conditions. We validate the model over a wide range of IVR topologies with silicon measurement and SPICE simulation. Finally, we present two case studies using architecture-level performance and power simulators. The first case study focuses on optimal PDS design for multi-core systems, which achieves 8.6% power efficiency improvement over conventional off-chip voltage regulator module\u2013 (VRM) based PDS. The second case study explores the design tradeoffs for IVR-assisted PDSs in CPU and GPU systems with fast per-core dynamic voltage and frequency scaling (DVFS). We find 2\n            <jats:italic>\u03bcs<\/jats:italic>\n            to be the optimal DVFS timescale, which not only reaps energy benefits (12.5% improvement in CPU and 50.0% improvement in GPU) but also avoids costly IVR overheads.\n          <\/jats:p>","DOI":"10.1145\/3468145","type":"journal-article","created":{"date-parts":[[2021,9,3]],"date-time":"2021-09-03T16:12:01Z","timestamp":1630685521000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System"],"prefix":"10.1145","volume":"18","author":[{"given":"An","family":"Zou","sequence":"first","affiliation":[{"name":"Shanghai Jiao Tong University, China, and Washington University in St. Louis, USA"}]},{"given":"Huifeng","family":"Zhu","sequence":"additional","affiliation":[{"name":"Washington University in St. Louis, USA"}]},{"given":"Jingwen","family":"Leng","sequence":"additional","affiliation":[{"name":"Shanghai Jiao Tong University, China"}]},{"given":"Xin","family":"He","sequence":"additional","affiliation":[{"name":"University of Michigan, USA"}]},{"given":"Vijay Janapa","family":"Reddi","sequence":"additional","affiliation":[{"name":"Harvard University, USA"}]},{"given":"Christopher D.","family":"Gill","sequence":"additional","affiliation":[{"name":"Washington University in St. Louis, USA"}]},{"given":"Xuan","family":"Zhang","sequence":"additional","affiliation":[{"name":"Washington University in St. Louis, USA"}]}],"member":"320","published-online":{"date-parts":[[2021,9,3]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2007.909288"},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.900281"},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201914)","author":"Andersen Toke Meyer","year":"2014","unstructured":"Toke Meyer Andersen , Florian Krismer , Johann Walter Kolar , Thomas Toifl , Christian Menolfi , Lukas Kull , Thomas Morf , Marcel Kossel , Matthias Br\u00e4ndli , Peter Buchmann , et\u00a0al. 2014 . 4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7 W\/mm 2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS . 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