{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T22:24:14Z","timestamp":1771626254924,"version":"3.50.1"},"reference-count":283,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2021,9,13]],"date-time":"2021-09-13T00:00:00Z","timestamp":1631491200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSF\/Intel CAPA","award":["1723715"],"award-info":[{"award-number":["1723715"]}]},{"name":"NSERC Discovery","award":["RGPIN-2019-04613, and DGECR-2019-00120"],"award-info":[{"award-number":["RGPIN-2019-04613, and DGECR-2019-00120"]}]},{"name":"Canada Foundation for Innovation John R. Evans Leaders Fund"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2021,12,31]]},"abstract":"<jats:p>FPGA-based accelerators are increasingly popular across a broad range of applications, because they offer massive parallelism, high energy efficiency, and great flexibility for customizations. However, difficulties in programming and integrating FPGAs have hindered their widespread adoption. Since the mid 2000s, there has been extensive research and development toward making FPGAs accessible to software-inclined developers, besides hardware specialists. Many programming models and automated synthesis tools, such as high-level synthesis, have been proposed to tackle this grand challenge. In this survey, we describe the progression and future prospects of the ongoing journey in significantly improving the software programmability of FPGAs. We first provide a taxonomy of the essential techniques for building a high-performance FPGA accelerator, which requires customizations of the compute engines, memory hierarchy, and data representations. We then summarize a rich spectrum of work on programming abstractions and optimizing compilers that provide different trade-offs between performance and productivity. Finally, we highlight several additional challenges and opportunities that deserve extra attention by the community to bring FPGA-based computing to the masses.<\/jats:p>","DOI":"10.1145\/3469660","type":"journal-article","created":{"date-parts":[[2021,9,14]],"date-time":"2021-09-14T00:51:51Z","timestamp":1631580711000},"page":"1-39","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":34,"title":["Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects"],"prefix":"10.1145","volume":"14","author":[{"given":"Yi-Hsiang","family":"Lai","sequence":"first","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}]},{"given":"Ecenur","family":"Ustun","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}]},{"given":"Shaojie","family":"Xiang","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}]},{"given":"Zhenman","family":"Fang","sequence":"additional","affiliation":[{"name":"Simon Fraser University, Burnaby, BC, Canada"}]},{"given":"Hongbo","family":"Rong","sequence":"additional","affiliation":[{"name":"Intel, Santa Clara, CA, USA"}]},{"given":"Zhiru","family":"Zhang","sequence":"additional","affiliation":[{"name":"Cornell University, Ithaca, NY, USA"}]}],"member":"320","published-online":{"date-parts":[[2021,9,13]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"et\u00a0al","author":"Abadi Mart\u00edn","year":"2016","unstructured":"Mart\u00edn Abadi , Ashish Agarwal , Paul Barham , Eugene Brevdo , Zhifeng Chen , Craig Citro , Greg S. Corrado , Andy Davis , Jeffrey Dean , Matthieu Devin , et\u00a0al . 2016 . Tensorflow : Large-scale machine learning on heterogeneous distributed systems. Retrieved from https:\/\/arXiv:1603.04467. Mart\u00edn Abadi, Ashish Agarwal, Paul Barham, Eugene Brevdo, Zhifeng Chen, Craig Citro, Greg S. Corrado, Andy Davis, Jeffrey Dean, Matthieu Devin, et\u00a0al. 2016. Tensorflow: Large-scale machine learning on heterogeneous distributed systems. Retrieved from https:\/\/arXiv:1603.04467."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629442"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00077"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950421"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03034-5_13"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847273"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488796"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.5555\/3314872.3314896"},{"key":"e_1_2_1_9_1","volume-title":"Anderson","author":"Bansal Samridhi","year":"2018","unstructured":"Samridhi Bansal , Hsuan Hsiao , Tomasz Czajkowski , and Jason H . Anderson . 2018 . High-level synthesis of software-customizable floating-point cores. In Proceedings of the Design, Automation, and Test in Europe (DATE '18). Samridhi Bansal, Hsuan Hsiao, Tomasz Czajkowski, and Jason H. Anderson. 2018. High-level synthesis of software-customizable floating-point cores. In Proceedings of the Design, Automation, and Test in Europe (DATE'18)."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.5555\/1025127.1025992"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1556444.1556449"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/324133.324234"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.32"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145726"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1379022.1375595"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1229428.1229446"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.25"},{"key":"e_1_2_1_18_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'17)","author":"Bussa Pavan Kumar","unstructured":"Pavan Kumar Bussa , Jeffrey Goeders , and Steven J. E. Wilton . 2017. Accelerating In-System FPGA debug of high-level synthesis circuits using incremental compilation techniques . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'17) . Pavan Kumar Bussa, Jeffrey Goeders, and Steven J. E. Wilton. 2017. Accelerating In-System FPGA debug of high-level synthesis circuits using incremental compilation techniques. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'17)."},{"key":"e_1_2_1_19_1","unstructured":"Cadence. 2020. Stratus High-Level Synthesis. Retrieved from https:\/\/www.cadence.com\/content\/dam\/cadence-www\/global\/en_US\/documents\/tools\/digital-design-signoff\/stratus-ds.pdf.  Cadence. 2020. Stratus High-Level Synthesis. Retrieved from https:\/\/www.cadence.com\/content\/dam\/cadence-www\/global\/en_US\/documents\/tools\/digital-design-signoff\/stratus-ds.pdf."},{"key":"e_1_2_1_20_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14)","author":"Calagar Nazanin","unstructured":"Nazanin Calagar , Stephen D. Brown , and Jason H. Anderson . 2014. Source-level debugging for FPGA high-level synthesis . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14) . 1\u20138. Nazanin Calagar, Stephen D. Brown, and Jason H. Anderson. 2014. Source-level debugging for FPGA high-level synthesis. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14). 1\u20138."},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/2485288.2485338"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14)","author":"Canis Andrew","unstructured":"Andrew Canis , Stephen D. Brown , and Jason H. Anderson . 2014. Modulo SDC scheduling with recurrence minimization in high-level synthesis . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14) . Andrew Canis, Stephen D. Brown, and Jason H. Anderson. 2014. Modulo SDC scheduling with recurrence minimization in high-level synthesis. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14)."},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.5555\/2555729.2555747"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715262"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195647"},{"key":"e_1_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.5555\/3291168.3291211"},{"key":"e_1_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00014"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195694"},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00020"},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2497259"},{"key":"e_1_2_1_32_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'17)","author":"Chen Yu Ting","unstructured":"Yu Ting Chen and Jason H. Anderson . 2017. Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'17) . Yu Ting Chen and Jason H. Anderson. 2017. Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'17)."},{"key":"e_1_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.5555\/3027041.3027052"},{"key":"e_1_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375297"},{"key":"e_1_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240850"},{"key":"e_1_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439470"},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718365"},{"key":"e_1_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.13"},{"key":"e_1_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439301"},{"key":"e_1_2_1_40_1","volume-title":"FLASH: Fast, parallel, and accurate simulator for HLS","author":"Choi Young-Kyu","year":"2020","unstructured":"Young-Kyu Choi , Yuze Chi , Jie Wang , and Jason Cong . 2020 . FLASH: Fast, parallel, and accurate simulator for HLS . IEEE Trans. Comput.-Aided Design Integr. Circ. Syst . (2020). Young-Kyu Choi, Yuze Chi, Jie Wang, and Jason Cong. 2020. FLASH: Fast, parallel, and accurate simulator for HLS. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. (2020)."},{"key":"e_1_2_1_41_1","volume-title":"Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'17)","author":"Jason Cong Choi","year":"2017","unstructured":"Young-kyu Choi and Jason Cong . 2017 . HLScope: High-level performance debugging for FPGA designs . In Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'17) . Young-kyu Choi and Jason Cong. 2017. HLScope: High-level performance debugging for FPGA designs. In Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'17)."},{"key":"e_1_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240815"},{"key":"e_1_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897972"},{"key":"e_1_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3294054"},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199792"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950420"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950435"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2675359"},{"key":"e_1_2_1_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/1088149.1088169"},{"key":"e_1_2_1_50_1","volume-title":"Chen Zhang, and Peipei Zhou.","author":"Cong Jason","year":"2018","unstructured":"Jason Cong , Zhenman Fang , Yuchen Hao , Peng Wei , Cody Hao Yu , Chen Zhang, and Peipei Zhou. 2018 . Best-effort FPGA programming: A few steps can go a long way. Retrieved from https:\/\/arXiv:1807.01340. Jason Cong, Zhenman Fang, Yuchen Hao, Peng Wei, Cody Hao Yu, Chen Zhang, and Peipei Zhou. 2018. Best-effort FPGA programming: A few steps can go a long way. Retrieved from https:\/\/arXiv:1807.01340."},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2017.2741459"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2876372"},{"key":"e_1_2_1_53_1","volume-title":"Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'18)","author":"Cong Jason","year":"2018","unstructured":"Jason Cong , Zhenman Fang , Michael Lo , Hanrui Wang , Jingxian Xu , and Shaochong Zhang . 2018 . Understanding performance differences of FPGAs and GPUs . In Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'18) . Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, and Shaochong Zhang. 2018. Understanding performance differences of FPGAs and GPUs. In Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'18)."},{"key":"e_1_2_1_54_1","doi-asserted-by":"crossref","unstructured":"Jason Cong Muhuan Huang Peichen Pan Yuxin Wang and Peng Zhang. 2016. Source-to-source optimization for HLS. FPGAs Softw. Program. (2016).  Jason Cong Muhuan Huang Peichen Pan Yuxin Wang and Peng Zhang. 2016. Source-to-source optimization for HLS. FPGAs Softw. Program. (2016).","DOI":"10.1007\/978-3-319-26408-0_8"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/1929943.1929947"},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488491"},{"key":"e_1_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"e_1_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240838"},{"key":"e_1_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3195999"},{"key":"e_1_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062208"},{"key":"e_1_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00028"},{"key":"e_1_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147025"},{"key":"e_1_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878966"},{"key":"e_1_2_1_64_1","volume-title":"GAUT: A high-level synthesis tool for DSP applications. High-Level Synth.","author":"Coussy Philippe","year":"2008","unstructured":"Philippe Coussy , Cyrille Chavet , Pierre Bomel , Dominique Heller , Eric Senn , and Eric Martin . 2008 . GAUT: A high-level synthesis tool for DSP applications. High-Level Synth. (2008). Philippe Coussy, Cyrille Chavet, Pierre Bomel, Dominique Heller, Eric Senn, and Eric Martin. 2008. GAUT: A high-level synthesis tool for DSP applications. High-Level Synth. (2008)."},{"key":"e_1_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/1661438.1661443"},{"key":"e_1_2_1_66_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'12)","author":"Czajkowski Tomasz S.","unstructured":"Tomasz S. Czajkowski , Utku Aydonat , Dmitry Denisenko , John Freeman , Michael Kinsner , David Neto , Jason Wong , Peter Yiannacouras , and Deshanand P. Singh . 2012. From OpenCL to high-performance hardware on FPGAs . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'12) . Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras, and Deshanand P. Singh. 2012. From OpenCL to high-performance hardware on FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'12)."},{"key":"e_1_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847339"},{"key":"e_1_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174268"},{"key":"e_1_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2017.8335152"},{"key":"e_1_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593143"},{"key":"e_1_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021754"},{"key":"e_1_2_1_72_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00029"},{"key":"e_1_2_1_73_1","doi-asserted-by":"crossref","unstructured":"Luka Daoud Dawid Zydek and Henry Selvaraj. 2014. A survey of high level synthesis languages tools and compilers for reconfigurable high performance computing. Adv. Syst. Sci. (2014).  Luka Daoud Dawid Zydek and Henry Selvaraj. 2014. A survey of high level synthesis languages tools and compilers for reconfigurable high performance computing. Adv. Syst. Sci. (2014).","DOI":"10.1007\/978-3-319-01857-7_47"},{"key":"e_1_2_1_74_1","volume-title":"et\u00a0al","author":"Rouhani Bita Darvish","year":"2020","unstructured":"Bita Darvish Rouhani , Daniel Lo , Ritchie Zhao , Ming Liu , Jeremy Fowers , Kalin Ovtcharov , Anna Vinogradsky , Sarah Massengill , Lita Yang , Ray Bittner , et\u00a0al . 2020 . Pushing the limits of narrow precision inferencing at cloud scale with microsoft floating point. Adv. Neural Info. Process. Syst . (2020). Bita Darvish Rouhani, Daniel Lo, Ritchie Zhao, Ming Liu, Jeremy Fowers, Kalin Ovtcharov, Anna Vinogradsky, Sarah Massengill, Lita Yang, Ray Bittner, et\u00a0al. 2020. Pushing the limits of narrow precision inferencing at cloud scale with microsoft floating point. Adv. Neural Info. Process. Syst. (2020)."},{"key":"e_1_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2011.44"},{"key":"e_1_2_1_76_1","unstructured":"Luiz Henrique De Figueiredo and Jorge Stolfi. 2004. Affine arithmetic: Concepts and applications. Numer. Algor. (2004).  Luiz Henrique De Figueiredo and Jorge Stolfi. 2004. Affine arithmetic: Concepts and applications. Numer. Algor. (2004)."},{"key":"e_1_2_1_77_1","unstructured":"Johannes de Fine Licht Simon Meierhans and Torsten Hoefler. 2018. Transformations of high-level synthesis codes for high-performance computing. Retrieved from https:\/\/arXiv:1805.08288.  Johannes de Fine Licht Simon Meierhans and Torsten Hoefler. 2018. Transformations of high-level synthesis codes for high-performance computing. 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Janneck. 2003. CAL language report: Specification of the CAL actor language. ERL Tech. Memo UCB\/ERL (2003).  Johan Eker and J. Janneck. 2003. CAL language report: Specification of the CAL actor language. ERL Tech. Memo UCB\/ERL (2003)."},{"key":"e_1_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1145\/3241045"},{"key":"e_1_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2019.00013"},{"key":"e_1_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012750"},{"key":"e_1_2_1_86_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126564"},{"key":"e_1_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927481"},{"key":"e_1_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00012"},{"key":"e_1_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1145\/3375899"},{"key":"e_1_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00018"},{"key":"e_1_2_1_91_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14)","author":"Goeders Jeffrey","unstructured":"Jeffrey Goeders and Steven J. E. Wilton . 2014. Effective FPGA debug for high-level synthesis generated circuits . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14) . Jeffrey Goeders and Steven J. E. Wilton. 2014. Effective FPGA debug for high-level synthesis generated circuits. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14)."},{"key":"e_1_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2565204"},{"key":"e_1_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.27"},{"key":"e_1_2_1_94_1","volume-title":"Proceedings of the International Conference on Field Programmable Technology (FPT'10)","author":"Gort Marcel","unstructured":"Marcel Gort and Jason H. Anderson . 2010. Deterministic multi-core parallel routing for FPGAs . In Proceedings of the International Conference on Field Programmable Technology (FPT'10) . Marcel Gort and Jason H. Anderson. 2010. Deterministic multi-core parallel routing for FPGAs. In Proceedings of the International Conference on Field Programmable Technology (FPT'10)."},{"key":"e_1_2_1_95_1","volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'13)","author":"Gort Marcel","unstructured":"Marcel Gort and Jason H. Anderson . 2013. Range and bitmask analysis for hardware optimization in high-level synthesis . In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'13) . Marcel Gort and Jason H. Anderson. 2013. Range and bitmask analysis for hardware optimization in high-level synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'13)."},{"key":"e_1_2_1_96_1","unstructured":"Ian Gray Yu Chan Jamie Garside Neil Audsley and Andy Wellings. 2015. Transparent hardware synthesis of Java for predictable large-scale distributed systems. Retrieved from https:\/\/arXiv:1508.07142.  Ian Gray Yu Chan Jamie Garside Neil Audsley and Andy Wellings. 2015. Transparent hardware synthesis of Java for predictable large-scale distributed systems. Retrieved from https:\/\/arXiv:1508.07142."},{"key":"e_1_2_1_97_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2013.6567545"},{"key":"e_1_2_1_98_1","doi-asserted-by":"crossref","unstructured":"Tobias Grosser Armin Groesslinger and Christian Lengauer. 2012. Polly\u2013performing polyhedral optimizations on a low-level intermediate representation. Parallel Process. Lett. (2012).  Tobias Grosser Armin Groesslinger and Christian Lengauer. 2012. Polly\u2013performing polyhedral optimizations on a low-level intermediate representation. Parallel Process. Lett. (2012).","DOI":"10.1142\/S0129626412500107"},{"key":"e_1_2_1_99_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2957819"},{"key":"e_1_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439289"},{"key":"e_1_2_1_101_1","doi-asserted-by":"publisher","DOI":"10.5555\/3437539.3437574"},{"key":"e_1_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00027"},{"key":"e_1_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00016"},{"key":"e_1_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.1145\/3075620"},{"key":"e_1_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865091"},{"key":"e_1_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78610-8_30"},{"key":"e_1_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1145\/2601097.2601174"},{"key":"e_1_2_1_108_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897824.2925892"},{"key":"e_1_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1145\/502102.502106"},{"key":"e_1_2_1_110_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293922"},{"key":"e_1_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174246"},{"key":"e_1_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450105"},{"key":"e_1_2_1_113_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317924"},{"key":"e_1_2_1_114_1","doi-asserted-by":"publisher","DOI":"10.1109\/IMSNA.2013.6743419"},{"key":"e_1_2_1_115_1","doi-asserted-by":"publisher","DOI":"10.1145\/2987550.2987569"},{"key":"e_1_2_1_116_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021749"},{"key":"e_1_2_1_117_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435296"},{"key":"e_1_2_1_118_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293924"},{"key":"e_1_2_1_119_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2954472"},{"key":"e_1_2_1_120_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00034"},{"key":"e_1_2_1_121_1","unstructured":"Intel. 2019. Intel Agilex F-Series FPGAs & SoCs. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/products\/programmable\/fpga\/agilex\/f-series.html.  Intel. 2019. Intel Agilex F-Series FPGAs & SoCs. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/products\/programmable\/fpga\/agilex\/f-series.html."},{"key":"e_1_2_1_122_1","unstructured":"Intel. 2020. Intel High Level Synthesis Compiler Pro Edition: Reference Manual. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/programmable\/documentation\/ewa1462824960255.html.  Intel. 2020. Intel High Level Synthesis Compiler Pro Edition: Reference Manual. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/programmable\/documentation\/ewa1462824960255.html."},{"key":"e_1_2_1_123_1","unstructured":"Intel. 2020. Intel SoC FPGAs. Retrieved from https:\/\/www.intel.ca\/content\/www\/ca\/en\/products\/programmable\/soc.html.  Intel. 2020. Intel SoC FPGAs. Retrieved from https:\/\/www.intel.ca\/content\/www\/ca\/en\/products\/programmable\/soc.html."},{"key":"e_1_2_1_124_1","unstructured":"Intel. 2020. The oneAPI Specification. Retrieved from https:\/\/www.oneapi.com\/.  Intel. 2020. The oneAPI Specification. Retrieved from https:\/\/www.oneapi.com\/."},{"key":"e_1_2_1_125_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1993.279483"},{"key":"e_1_2_1_126_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00027"},{"key":"e_1_2_1_127_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2013.02.021"},{"key":"e_1_2_1_128_1","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"e_1_2_1_129_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375313"},{"key":"e_1_2_1_130_1","doi-asserted-by":"publisher","DOI":"10.1145\/3126525"},{"key":"e_1_2_1_131_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174264"},{"key":"e_1_2_1_132_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293914"},{"key":"e_1_2_1_133_1","volume-title":"Juniper: Java Platform for High-performance and Real-time Large-scale Data.","year":"2020","unstructured":"Juniper. 2020 . Juniper: Java Platform for High-performance and Real-time Large-scale Data. Retrieved from http:\/\/ www.juniper-project.org\/. Juniper. 2020. Juniper: Java Platform for High-performance and Real-time Large-scale Data. Retrieved from http:\/\/ www.juniper-project.org\/."},{"key":"e_1_2_1_134_1","volume-title":"Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'18)","author":"\u00a0al Nachiket Kapre","year":"2018","unstructured":"Nachiket Kapre et \u00a0al . 2018 . Hoplite-Q: Priority-aware routing in FPGA overlay NoCs . In Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'18) . Nachiket Kapre et\u00a0al. 2018. Hoplite-Q: Priority-aware routing in FPGA overlay NoCs. In Proceedings of the IEEE Symposium on Field Programmable Custom Computing Machines (FCCM'18)."},{"key":"e_1_2_1_135_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2015.7293956"},{"key":"e_1_2_1_136_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847266"},{"key":"e_1_2_1_137_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICAC.2018.00021"},{"key":"e_1_2_1_138_1","unstructured":"Ryan Kastner Janarbek Matai and Stephen Neuendorffer. 2018. Parallel programming for FPGAs. Retrieved from https:\/\/arXiv:1805.03648.  Ryan Kastner Janarbek Matai and Stephen Neuendorffer. 2018. Parallel programming for FPGAs. Retrieved from https:\/\/arXiv:1805.03648."},{"key":"e_1_2_1_139_1","unstructured":"Keras. 2020. Keras. Simple. Flexible. Powerful.Retrieved from https:\/\/keras.io\/.  Keras. 2020. Keras. Simple. Flexible. Powerful.Retrieved from https:\/\/keras.io\/."},{"key":"e_1_2_1_140_1","doi-asserted-by":"publisher","DOI":"10.1145\/3204919.3204937"},{"key":"e_1_2_1_141_1","doi-asserted-by":"publisher","DOI":"10.5555\/3291168.3291177"},{"key":"e_1_2_1_142_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174260"},{"key":"e_1_2_1_143_1","doi-asserted-by":"crossref","unstructured":"Jeffrey Kingyens and J. Gregory Steffan. 2011. The potential for a GPU-Like overlay architecture for FPGAs. Intl. J. Reconfig. Comput. (2011).  Jeffrey Kingyens and J. Gregory Steffan. 2011. The potential for a GPU-Like overlay architecture for FPGAs. Intl. J. Reconfig. Comput. (2011).","DOI":"10.1155\/2011\/514581"},{"key":"e_1_2_1_144_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874889"},{"key":"e_1_2_1_145_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133901"},{"key":"e_1_2_1_146_1","volume-title":"Proceedings of the International Conference on Field Programmable Technology (FPT'13)","author":"Klimovic Ana","unstructured":"Ana Klimovic and Jason H. Anderson . 2013. Bitwidth-optimized hardware accelerators with software fallback . In Proceedings of the International Conference on Field Programmable Technology (FPT'13) . Ana Klimovic and Jason H. Anderson. 2013. Bitwidth-optimized hardware accelerators with software fallback. In Proceedings of the International Conference on Field Programmable Technology (FPT'13)."},{"key":"e_1_2_1_147_1","doi-asserted-by":"publisher","DOI":"10.1145\/3296979.3192379"},{"key":"e_1_2_1_148_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001150"},{"key":"e_1_2_1_149_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650320"},{"key":"e_1_2_1_150_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293910"},{"key":"e_1_2_1_151_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415644"},{"key":"e_1_2_1_152_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00030"},{"key":"e_1_2_1_153_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.873887"},{"key":"e_1_2_1_154_1","volume-title":"Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines.","author":"Lewis David M.","unstructured":"David M. Lewis , Marcus H. van Ierssel , and Daniel H. Wong . 1993. A field programmable accelerator for compiled-code applications . In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines. David M. Lewis, Marcus H. van Ierssel, and Daniel H. Wong. 1993. A field programmable accelerator for compiled-code applications. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines."},{"key":"e_1_2_1_155_1","volume-title":"Proceedings of the International Workshop on Polyhedral Compilation Techniques (IMPACT'14)","author":"Li Peng","year":"2014","unstructured":"Peng Li , Louis-No\u00ebl Pouchet , and Jason Cong . 2014 . Throughput optimization for high-level synthesis using resource constraints . In Proceedings of the International Workshop on Polyhedral Compilation Techniques (IMPACT'14) . Peng Li, Louis-No\u00ebl Pouchet, and Jason Cong. 2014. Throughput optimization for high-level synthesis using resource constraints. In Proceedings of the International Workshop on Polyhedral Compilation Techniques (IMPACT'14)."},{"key":"e_1_2_1_156_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199827"},{"key":"e_1_2_1_157_1","volume-title":"FP-BNN: Binarized neural network on FPGA. Neurocomputing","author":"Liang Shuang","year":"2018","unstructured":"Shuang Liang , Shouyi Yin , Leibo Liu , Wayne Luk , and Shaojun Wei . 2018. FP-BNN: Binarized neural network on FPGA. Neurocomputing ( 2018 ). Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, and Shaojun Wei. 2018. FP-BNN: Binarized neural network on FPGA. Neurocomputing (2018)."},{"key":"e_1_2_1_158_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3003843"},{"key":"e_1_2_1_159_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.31"},{"key":"e_1_2_1_160_1","doi-asserted-by":"publisher","DOI":"10.1145\/3392717.3392757"},{"key":"e_1_2_1_161_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2783363"},{"key":"e_1_2_1_162_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00018"},{"key":"e_1_2_1_163_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.19"},{"key":"e_1_2_1_164_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577358"},{"key":"e_1_2_1_165_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00054"},{"key":"e_1_2_1_166_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00033"},{"key":"e_1_2_1_167_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439284"},{"key":"e_1_2_1_168_1","doi-asserted-by":"publisher","DOI":"10.1145\/1970353.1970355"},{"key":"e_1_2_1_169_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344676"},{"key":"e_1_2_1_170_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00059"},{"key":"e_1_2_1_171_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2014.2360030"},{"key":"e_1_2_1_172_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446050"},{"key":"e_1_2_1_173_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'19)","author":"Makrani Hosein Mohammadi","year":"2019","unstructured":"Hosein Mohammadi Makrani , Farnoud Farahmand , Hossein Sayadi , Sara Bondi , Sai Manoj Pudukotai Dinakarrao , Houman Homayoun , and Setareh Rafatirad . 2019 . Pyramid: Machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'19) . Hosein Mohammadi Makrani, Farnoud Farahmand, Hossein Sayadi, Sara Bondi, Sai Manoj Pudukotai Dinakarrao, Houman Homayoun, and Setareh Rafatirad. 2019. Pyramid: Machine learning framework to estimate the optimal timing and resource usage of a high-level synthesis design. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'19)."},{"key":"e_1_2_1_174_1","unstructured":"Maxeler. 2020. Maxeler High-performance Dataflow Computing Systems. Retrieved from https:\/\/www.maxeler.com\/products\/software\/maxcompiler\/.  Maxeler. 2020. Maxeler High-performance Dataflow Computing Systems. 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Retrieved from https:\/\/download-soc.microsemi.com\/FPGA\/HLS-EAP\/docs\/legup-9.1-docs\/index.html."},{"key":"e_1_2_1_180_1","unstructured":"Microchip. 2020. Microchip Acquires High-Level Synthesis Tool Provider LegUp to Simplify Development of PolarFire FPGA-based Edge Compute Solutions. Retrieved from https:\/\/www.microchip.com\/en-us\/about\/news-releases\/products\/microchip-acquires-high-level-synthesis-tool-provider-legup.  Microchip. 2020. Microchip Acquires High-Level Synthesis Tool Provider LegUp to Simplify Development of PolarFire FPGA-based Edge Compute Solutions. Retrieved from https:\/\/www.microchip.com\/en-us\/about\/news-releases\/products\/microchip-acquires-high-level-synthesis-tool-provider-legup."},{"key":"e_1_2_1_181_1","unstructured":"Microsoft. 2020. A Microsoft Custom Data Type for Efficient Inference. Retrieved from https:\/\/www.microsoft.com\/en-us\/research\/blog\/a-microsoft-custom-data-type-for-efficient-inference\/.  Microsoft. 2020. A Microsoft Custom Data Type for Efficient Inference. Retrieved from https:\/\/www.microsoft.com\/en-us\/research\/blog\/a-microsoft-custom-data-type-for-efficient-inference\/."},{"key":"e_1_2_1_182_1","doi-asserted-by":"publisher","DOI":"10.1145\/2159542.2159547"},{"key":"e_1_2_1_183_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00011"},{"key":"e_1_2_1_184_1","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14)","author":"Joshua","unstructured":"Joshua S. Monson and Brad Hutchings. 2014. New approaches for in-system debug of behaviorally synthesized FPGA circuits . In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14) . Joshua S. Monson and Brad Hutchings. 2014. New approaches for in-system debug of behaviorally synthesized FPGA circuits. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL'14)."},{"key":"e_1_2_1_185_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689087"},{"key":"e_1_2_1_186_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2018.02.012"},{"key":"e_1_2_1_187_1","volume-title":"VTA: An open hardware-software stack for deep learning.","author":"Moreau Thierry","year":"2018","unstructured":"Thierry Moreau , Tianqi Chen , Ziheng Jiang , Luis Ceze , Carlos Guestrin , and Arvind Krishnamurthy . 2018 . VTA: An open hardware-software stack for deep learning. Retrieved from https:\/\/arXiv:1807.04188. Thierry Moreau, Tianqi Chen, Ziheng Jiang, Luis Ceze, Carlos Guestrin, and Arvind Krishnamurthy. 2018. VTA: An open hardware-software stack for deep learning. Retrieved from https:\/\/arXiv:1807.04188."},{"key":"e_1_2_1_188_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2228270"},{"key":"e_1_2_1_189_1","volume-title":"SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs","author":"Murray Kevin E.","year":"2020","unstructured":"Kevin E. Murray , Mohamed A. Elgammal , Vaughn Betz , Tim Ansell , Keith Rothman , and Alessandro Comodi . 2020. SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs . IEEE Micro ( 2020 ). Kevin E. Murray, Mohamed A. Elgammal, Vaughn Betz, Tim Ansell, Keith Rothman, and Alessandro Comodi. 2020. SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs. IEEE Micro (2020)."},{"key":"e_1_2_1_190_1","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"e_1_2_1_191_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"},{"key":"e_1_2_1_192_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385974"},{"key":"e_1_2_1_193_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3024098"},{"key":"e_1_2_1_194_1","doi-asserted-by":"publisher","DOI":"10.5555\/2650280.2650336"},{"key":"e_1_2_1_195_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380730"},{"key":"e_1_2_1_196_1","first-page":"1","article-title":"A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios","volume":"1","author":"Ouedraogo Ganda Stephane","year":"2014","unstructured":"Ganda Stephane Ouedraogo , Matthieu Gautier , and Olivier Sentieys . 2014 . A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios . EURASIP J. Adv. Signal Process. 1 (2014), 1 \u2013 15 . Ganda Stephane Ouedraogo, Matthieu Gautier, and Olivier Sentieys. 2014. A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios. EURASIP J. Adv. Signal Process. 1 (2014), 1\u201315.","journal-title":"EURASIP J. Adv. Signal Process."},{"key":"e_1_2_1_197_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577357"},{"key":"e_1_2_1_198_1","volume-title":"Proceedings of the Symposium on Application Specific Processors (SASP'09)","author":"Papakonstantinou Alexandros","unstructured":"Alexandros Papakonstantinou , Karthik Gururaj , John A. Stratton , Deming Chen , Jason Cong , and Wen-Mei W. Hwu . 2009. FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs . In Proceedings of the Symposium on Application Specific Processors (SASP'09) . Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, and Wen-Mei W. Hwu. 2009. FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. In Proceedings of the Symposium on Application Specific Processors (SASP'09)."},{"key":"e_1_2_1_199_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375299"},{"key":"e_1_2_1_200_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00047"},{"key":"e_1_2_1_201_1","doi-asserted-by":"publisher","DOI":"10.5555\/3454287.3455008"},{"key":"e_1_2_1_202_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2015.7393356"},{"key":"e_1_2_1_203_1","volume-title":"Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW'18)","author":"Peverelli Francesco","unstructured":"Francesco Peverelli , Marco Rabozzi , Emanuele Del Sozzo , and Marco D. Santambrogio . 2018. OXiGen: A tool for automatic acceleration of C functions into dataflow FPGA-based kernels . In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW'18) . Francesco Peverelli, Marco Rabozzi, Emanuele Del Sozzo, and Marco D. Santambrogio. 2018. OXiGen: A tool for automatic acceleration of C functions into dataflow FPGA-based kernels. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops (IPDPSW'18)."},{"key":"e_1_2_1_204_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"e_1_2_1_205_1","volume-title":"Pier Luca Lanzi, and Donatella Sciuto","author":"Pilato Christian","year":"2010","unstructured":"Christian Pilato , Daniele Loiacono , Antonino Tumeo , Fabrizio Ferrandi , Pier Luca Lanzi, and Donatella Sciuto . 2010 . Speeding-Up expensive evaluations in high-level synthesis using solution modeling and fitness inheritance. Comput. Intell. Exp. Optimiz. Problems ( 2010). Christian Pilato, Daniele Loiacono, Antonino Tumeo, Fabrizio Ferrandi, Pier Luca Lanzi, and Donatella Sciuto. 2010. Speeding-Up expensive evaluations in high-level synthesis using solution modeling and fitness inheritance. Comput. Intell. Exp. Optimiz. Problems (2010)."},{"key":"e_1_2_1_206_1","volume-title":"Proceedings of the International Conference on Field Programmable Technology (FPT'16)","author":"Jose","unstructured":"Jose P. Pinilla and Steven J. E. Wilton. 2016. Enhanced source-level instrumentation for FPGA in-system debug of high-level synthesis designs . In Proceedings of the International Conference on Field Programmable Technology (FPT'16) . Jose P. Pinilla and Steven J. E. Wilton. 2016. Enhanced source-level instrumentation for FPGA in-system debug of high-level synthesis designs. In Proceedings of the International Conference on Field Programmable Technology (FPT'16)."},{"key":"e_1_2_1_207_1","doi-asserted-by":"publisher","DOI":"10.1145\/2435264.2435273"},{"key":"e_1_2_1_208_1","doi-asserted-by":"publisher","DOI":"10.1145\/3107953"},{"key":"e_1_2_1_209_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"e_1_2_1_210_1","doi-asserted-by":"publisher","DOI":"10.1145\/2499370.2462176"},{"key":"e_1_2_1_211_1","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"e_1_2_1_212_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199842"},{"key":"e_1_2_1_213_1","unstructured":"Hongbo Rong. 2017. Programmatic control of a compiler for generating high-performance spatial hardware. Retrieved from https:\/\/arXiv:1711.07606.  Hongbo Rong. 2017. Programmatic control of a compiler for generating high-performance spatial hardware. Retrieved from https:\/\/arXiv:1711.07606."},{"key":"e_1_2_1_214_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00011"},{"key":"e_1_2_1_215_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293913"},{"key":"e_1_2_1_216_1","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/162404"},{"key":"e_1_2_1_217_1","doi-asserted-by":"publisher","DOI":"10.5555\/598548.2813294"},{"key":"e_1_2_1_218_1","volume-title":"CAPH: A language for implementing stream-processing applications on FPGAs. Embed. Syst. Design FPGAs","author":"S\u00e9rot Jocelyn","year":"2013","unstructured":"Jocelyn S\u00e9rot , Fran\u00e7ois Berry , and Sameer Ahmed . 2013 . CAPH: A language for implementing stream-processing applications on FPGAs. Embed. Syst. Design FPGAs (2013). Jocelyn S\u00e9rot, Fran\u00e7ois Berry, and Sameer Ahmed. 2013. CAPH: A language for implementing stream-processing applications on FPGAs. Embed. Syst. Design FPGAs (2013)."},{"key":"e_1_2_1_219_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554774"},{"key":"e_1_2_1_220_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2012.55"},{"key":"e_1_2_1_221_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195659"},{"key":"e_1_2_1_222_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840836"},{"key":"e_1_2_1_223_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021732"},{"key":"e_1_2_1_224_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3035787"},{"key":"e_1_2_1_225_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00022"},{"key":"e_1_2_1_226_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375321"},{"key":"e_1_2_1_227_1","volume-title":"Ruhlov","author":"Solovyev Roman A.","year":"2018","unstructured":"Roman A. Solovyev , Alexandr A. Kalinin , Alexander G. Kustov , Dmitry V. Telpukhov , and Vladimir S . Ruhlov . 2018 . FPGA implementation of convolutional neural networks with fixed-point calculations. Retrieved from https:\/\/arXiv:1808.09945. Roman A. Solovyev, Alexandr A. Kalinin, Alexander G. Kustov, Dmitry V. Telpukhov, and Vladimir S. Ruhlov. 2018. FPGA implementation of convolutional neural networks with fixed-point calculations. Retrieved from https:\/\/arXiv:1808.09945."},{"key":"e_1_2_1_228_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00020"},{"key":"e_1_2_1_229_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00033"},{"key":"e_1_2_1_230_1","doi-asserted-by":"publisher","DOI":"10.1145\/3180481"},{"key":"e_1_2_1_231_1","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2019.00016"},{"key":"e_1_2_1_232_1","unstructured":"Synthesijer. 2020. Synthesijer GitHub. Retrieved from https:\/\/github.com\/synthesijer\/synthesijer.  Synthesijer. 2020. Synthesijer GitHub. Retrieved from https:\/\/github.com\/synthesijer\/synthesijer."},{"key":"e_1_2_1_233_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689063"},{"key":"e_1_2_1_234_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840831"},{"key":"e_1_2_1_235_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378495"},{"key":"e_1_2_1_236_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645597"},{"key":"e_1_2_1_237_1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2018.2822862"},{"key":"e_1_2_1_238_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415657"},{"key":"e_1_2_1_239_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00020"},{"key":"e_1_2_1_240_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2277978"},{"key":"e_1_2_1_241_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062230"},{"key":"e_1_2_1_242_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950445"},{"key":"e_1_2_1_243_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2901243"},{"key":"e_1_2_1_244_1","doi-asserted-by":"publisher","DOI":"10.1145\/3050220.3050234"},{"key":"e_1_2_1_245_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439292"},{"key":"e_1_2_1_246_1","volume-title":"BFloat16: The secret to high performance on cloud TPUs. Google Cloud Blog","author":"Wang Shibo","year":"2019","unstructured":"Shibo Wang and Pankaj Kanwar . 2019. BFloat16: The secret to high performance on cloud TPUs. Google Cloud Blog ( 2019 ). Shibo Wang and Pankaj Kanwar. 2019. BFloat16: The secret to high performance on cloud TPUs. Google Cloud Blog (2019)."},{"key":"e_1_2_1_247_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174253"},{"key":"e_1_2_1_248_1","doi-asserted-by":"publisher","DOI":"10.1145\/1839480.1839486"},{"key":"e_1_2_1_249_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00028"},{"key":"e_1_2_1_250_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554780"},{"key":"e_1_2_1_251_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488748"},{"key":"e_1_2_1_252_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2017.8280122"},{"key":"e_1_2_1_253_1","volume-title":"DLVM: A modern compiler infrastructure for deep learning systems.","author":"Wei Richard","year":"2017","unstructured":"Richard Wei , Lane Schwartz , and Vikram Adve . 2017 . DLVM: A modern compiler infrastructure for deep learning systems. Retrieved from https:\/\/arXiv:1711.03016. Richard Wei, Lane Schwartz, and Vikram Adve. 2017. DLVM: A modern compiler infrastructure for deep learning systems. Retrieved from https:\/\/arXiv:1711.03016."},{"key":"e_1_2_1_254_1","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062207"},{"key":"e_1_2_1_255_1","doi-asserted-by":"publisher","DOI":"10.1145\/1498765.1498785"},{"key":"e_1_2_1_256_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00026"},{"key":"e_1_2_1_257_1","unstructured":"Xilinx. 2012. ChipScope Pro Software and Cores (UG029). Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx14_7\/chipscope_pro_sw_cores_ug029.pdf.  Xilinx. 2012. ChipScope Pro Software and Cores (UG029). Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx14_7\/chipscope_pro_sw_cores_ug029.pdf."},{"key":"e_1_2_1_258_1","unstructured":"Xilinx. 2020. SDNet Packet Processor User Guide. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2017_1\/ug1012-sdnet-packet-processor.pdf.  Xilinx. 2020. SDNet Packet Processor User Guide. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2017_1\/ug1012-sdnet-packet-processor.pdf."},{"key":"e_1_2_1_259_1","unstructured":"Xilinx. 2020. Vitis High-Level Synthesis User Guide. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2020_2\/ug1399-vitis-hls.pdf.  Xilinx. 2020. Vitis High-Level Synthesis User Guide. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2020_2\/ug1399-vitis-hls.pdf."},{"key":"e_1_2_1_260_1","unstructured":"Xilinx. 2020. Zynq UltraScale+ MPSoC. Retrieved from https:\/\/www.xilinx.com\/products\/silicon-devices\/soc\/zynq-ultrascale-mpsoc.html.  Xilinx. 2020. Zynq UltraScale+ MPSoC. Retrieved from https:\/\/www.xilinx.com\/products\/silicon-devices\/soc\/zynq-ultrascale-mpsoc.html."},{"key":"e_1_2_1_261_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2930577"},{"key":"e_1_2_1_262_1","doi-asserted-by":"publisher","DOI":"10.1145\/3218603.3218615"},{"key":"e_1_2_1_263_1","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293902"},{"key":"e_1_2_1_264_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887921"},{"key":"e_1_2_1_265_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196109"},{"key":"e_1_2_1_266_1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344704"},{"key":"e_1_2_1_267_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.41"},{"key":"e_1_2_1_268_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375312"},{"key":"e_1_2_1_269_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378491"},{"key":"e_1_2_1_270_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_2_1_271_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2785257"},{"key":"e_1_2_1_272_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"},{"key":"e_1_2_1_273_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439296"},{"key":"e_1_2_1_274_1","doi-asserted-by":"publisher","DOI":"10.5555\/2561828.2561872"},{"key":"e_1_2_1_275_1","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199757"},{"key":"e_1_2_1_276_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714724"},{"key":"e_1_2_1_277_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021741"},{"key":"e_1_2_1_278_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744801"},{"key":"e_1_2_1_279_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021772"},{"key":"e_1_2_1_280_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898040"},{"key":"e_1_2_1_281_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2910068"},{"key":"e_1_2_1_282_1","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021734"},{"key":"e_1_2_1_283_1","doi-asserted-by":"publisher","DOI":"10.5555\/2555692.2555707"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3469660","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3469660","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:17:29Z","timestamp":1750191449000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3469660"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,13]]},"references-count":283,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2021,12,31]]}},"alternative-id":["10.1145\/3469660"],"URL":"https:\/\/doi.org\/10.1145\/3469660","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,9,13]]},"assertion":[{"value":"2021-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-09-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}