{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,1]],"date-time":"2026-03-01T05:07:22Z","timestamp":1772341642139,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":69,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,11]],"date-time":"2022-06-11T00:00:00Z","timestamp":1654905600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"SRC CRISP"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,18]]},"DOI":"10.1145\/3470496.3527435","type":"proceedings-article","created":{"date-parts":[[2022,5,31]],"date-time":"2022-05-31T19:06:01Z","timestamp":1654023961000},"page":"623-637","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Accelerating database analytic query workloads using an associative processor"],"prefix":"10.1145","author":[{"given":"Helena","family":"Caminal","sequence":"first","affiliation":[{"name":"Cornell University"}]},{"given":"Yannis","family":"Chronis","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison"}]},{"given":"Tianshu","family":"Wu","sequence":"additional","affiliation":[{"name":"Cornell University"}]},{"given":"Jignesh M.","family":"Patel","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison"}]},{"given":"Jos\u00e9 F.","family":"Mart\u00ednez","sequence":"additional","affiliation":[{"name":"Cornell University"}]}],"member":"320","published-online":{"date-parts":[[2022,6,11]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"[n.d.]. 7 nm lithography process. https:\/\/en.wikichip.org\/wiki\/7_nm_lithography_process  [n.d.]. 7 nm lithography process. https:\/\/en.wikichip.org\/wiki\/7_nm_lithography_process"},{"key":"e_1_3_2_1_2_1","unstructured":"[n.d.]. CACTI 6.5. https:\/\/github.com\/HewlettPackard\/cacti. Accessed: 2019-08-12.  [n.d.]. CACTI 6.5. https:\/\/github.com\/HewlettPackard\/cacti. Accessed: 2019-08-12."},{"key":"e_1_3_2_1_3_1","unstructured":"[n.d.]. Cortex-A53 - Microarchitectures - ARM. https:\/\/en.wikichip.org\/wiki\/arm_holdings\/microarchitectures\/cortex-a53.  [n.d.]. Cortex-A53 - Microarchitectures - ARM. https:\/\/en.wikichip.org\/wiki\/arm_holdings\/microarchitectures\/cortex-a53."},{"key":"e_1_3_2_1_4_1","volume-title":"Intel 64 and IA-32 Architectures Software Developer's Manual","unstructured":"[n.d.]. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference. Intel Corporation. 2015 . [n.d.]. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference. Intel Corporation. 2015."},{"key":"e_1_3_2_1_5_1","unstructured":"[n.d.]. riscv-toolchain GitHub repository. https:\/\/github.com\/riscv\/riscv-gnutoolchain.  [n.d.]. riscv-toolchain GitHub repository. https:\/\/github.com\/riscv\/riscv-gnutoolchain."},{"key":"e_1_3_2_1_6_1","unstructured":"[n.d.]. Samsung Exynos 5433. https:\/\/en.wikichip.org\/wiki\/samsung\/exynos\/5433.  [n.d.]. Samsung Exynos 5433. https:\/\/en.wikichip.org\/wiki\/samsung\/exynos\/5433."},{"key":"e_1_3_2_1_7_1","unstructured":"2021. Data Age 2025: The datasphere and data-readiness from edge to core. https:\/\/www.i-scoop.eu\/big-data-action-value-context\/data-age-2025-datasphere\/  2021. Data Age 2025: The datasphere and data-readiness from edge to core. https:\/\/www.i-scoop.eu\/big-data-action-value-context\/data-age-2025-datasphere\/"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2851141.2851144"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123985"},{"key":"e_1_3_2_1_10_1","volume-title":"2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 245--258","author":"Agrawal S. R.","unstructured":"S. R. Agrawal , S. Idicula , A. Raghavan , E. Vlachos , V. Govindaraju , V. Varadarajan , C. Balkesen , G. Giannikis , C. Roth , N. Agarwal , and E. Sedlar . 2017. A Many-core Architecture for In-Memory Data Processing . In 2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 245--258 . S. R. Agrawal, S. Idicula, A. Raghavan, E. Vlachos, V. Govindaraju, V. Varadarajan, C. Balkesen, G. Giannikis, C. Roth, N. Agarwal, and E. Sedlar. 2017. A Many-core Architecture for In-Memory Data Processing. In 2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 245--258."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541956"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3183713.3190655"},{"key":"e_1_3_2_1_13_1","first-page":"414","article-title":"DBC: A Database Computer for Very Large Databases","volume":"28","author":"Banerjee Jayanta","year":"1979","unstructured":"Jayanta Banerjee , David K. Hsiao , and Krishnamurthi Kannan . 1979 . DBC: A Database Computer for Very Large Databases . IEEE Computer Architecture Letters 28 , 06 (1979), 414 -- 429 . Jayanta Banerjee, David K. Hsiao, and Krishnamurthi Kannan. 1979. DBC: A Database Computer for Very Large Databases. IEEE Computer Architecture Letters 28, 06 (1979), 414--429.","journal-title":"IEEE Computer Architecture Letters"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/1989323.1989328"},{"key":"e_1_3_2_1_15_1","volume-title":"CAPE: A Content-Addressable Processing Engine. In 2021 IEEE 27th International Symposium on High Performance Computer Architecture.","author":"Caminal H.","unstructured":"H. Caminal , K. Yang , S. Srinivasa , A. K. Ramanathan , K. Al-Hawaj , T. Wu , V. Narayanan , C. Batten , and J. F. Mart\u00ednez . 2021 . CAPE: A Content-Addressable Processing Engine. In 2021 IEEE 27th International Symposium on High Performance Computer Architecture. H. Caminal, K. Yang, S. Srinivasa, A. K. Ramanathan, K. Al-Hawaj, T. Wu, V. Narayanan, C. Batten, and J. F. Mart\u00ednez. 2021. CAPE: A Content-Addressable Processing Engine. In 2021 IEEE 27th International Symposium on High Performance Computer Architecture."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.14778\/1454159.1454171"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485945"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/69.50905"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"e_1_3_2_1_20_1","volume-title":"1992 Proceedings of the IEEE Custom Integrated Circuits Conference.","author":"Elliott D. G.","unstructured":"D. G. Elliott , W. M. Snelgrove , and M. Stumm . 1992. Computational RAM: A Memory-SIMD Hybrid and its Application to DSP . In 1992 Proceedings of the IEEE Custom Integrated Circuits Conference. D. G. Elliott, W. M. Snelgrove, and M. Stumm. 1992. Computational RAM: A Memory-SIMD Hybrid and its Application to DSP. In 1992 Proceedings of the IEEE Custom Integrated Circuits Conference."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"crossref","unstructured":"D. G. Elliott M. Stumm W. M. Snelgrove C. Cojocaru and R. Mckenzie. 1999. Computational RAM: implementing processors in memory. IEEE Design Test of Computers (1999).  D. G. Elliott M. Stumm W. M. Snelgrove C. Cojocaru and R. Mckenzie. 1999. Computational RAM: implementing processors in memory. IEEE Design Test of Computers (1999).","DOI":"10.1109\/54.748803"},{"key":"e_1_3_2_1_22_1","volume-title":"Content Addressable Parallel Processors","author":"Foster Caxton C.","unstructured":"Caxton C. Foster . 1976. Content Addressable Parallel Processors . John Wiley & Sons, Inc. Caxton C. Foster. 1976. Content Addressable Parallel Processors. John Wiley & Sons, Inc."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.14778\/3407790.3407797"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3076113.3076119"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"M. Gokhale B. Holmes and K. Iobst. 1995. Processing in memory: the Terasys massively parallel PIM array. Computer (1995).  M. Gokhale B. Holmes and K. Iobst. 1995. Processing in memory: the Terasys massively parallel PIM array. Computer (1995).","DOI":"10.1109\/2.375174"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/1142473.1142511"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/152610.152611"},{"key":"e_1_3_2_1_28_1","volume-title":"Data compression and database performance","author":"Graefe Goetz","unstructured":"Goetz Graefe and Leonard D Shapiro . 1990. Data compression and database performance . University of Colorado , Boulder, Department of Computer Science. Goetz Graefe and Leonard D Shapiro. 1990. Data compression and database performance. University of Colorado, Boulder, Department of Computer Science."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446749"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/1376616.1376670"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2806777.2806836"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2012.6189209"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/115790.115835"},{"key":"e_1_3_2_1_34_1","first-page":"49","article-title":"The Glass Half Full: Using Programmable Hardware Accelerators in Analytics","volume":"42","author":"Istv\u00e1n Zsolt","year":"2019","unstructured":"Zsolt Istv\u00e1n . 2019 . The Glass Half Full: Using Programmable Hardware Accelerators in Analytics . IEEE Data Eng. Bull. 42 , 1 (2019), 49 -- 60 . Zsolt Istv\u00e1n. 2019. The Glass Half Full: Using Programmable Hardware Accelerators in Analytics. IEEE Data Eng. Bull. 42, 1 (2019), 49--60.","journal-title":"IEEE Data Eng. Bull."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750412"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2236584.2236592"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.14778\/1687553.1687564"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1994.108"},{"key":"e_1_3_2_1_39_1","volume-title":"Summarizer: Trading Communication with Computing Near Storage. In 2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 219--231","author":"Koo G.","unstructured":"G. Koo , K. K. Matam , T. I., H. V. K. G. Narra , J. Li , H. Tseng , S. Swanson , and M. Annavaram . 2017 . Summarizer: Trading Communication with Computing Near Storage. In 2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 219--231 . G. Koo, K. K. Matam, T. I., H. V. K. G. Narra, J. Li, H. Tseng, S. Swanson, and M. Annavaram. 2017. Summarizer: Trading Communication with Computing Near Storage. In 2017 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 219--231."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.14778\/2850583.2850594"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00052"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012860"},{"key":"e_1_3_2_1_43_1","volume-title":"Master of None Acceleration: A Comparison of Accelerator Architectures for Analytical Query Processing. In 2019 ACM\/IEEE 46th Annual International Symposium on Computer Architecture (ISCA). 762--773","author":"Lottarini A.","unstructured":"A. Lottarini , J. P. Cerqueira , T. J. Repetti , S. A. Edwards , K. A. Ross , M. Seok , and M. A. Kim . 2019 . Master of None Acceleration: A Comparison of Accelerator Architectures for Analytical Query Processing. In 2019 ACM\/IEEE 46th Annual International Symposium on Computer Architecture (ISCA). 762--773 . A. Lottarini, J. P. Cerqueira, T. J. Repetti, S. A. Edwards, K. A. Ross, M. Seok, and M. A. Kim. 2019. Master of None Acceleration: A Comparison of Accelerator Architectures for Analytical Query Processing. In 2019 ACM\/IEEE 46th Annual International Symposium on Computer Architecture (ISCA). 762--773."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3318464.3389705"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2000.854387"},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"crossref","unstructured":"Amir Morad Leonid Yavits Shahar Kvatinsky and Ran Ginosar. 2016. Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. (2016).  Amir Morad Leonid Yavits Shahar Kvatinsky and Ran Ginosar. 2016. Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. (2016).","DOI":"10.1145\/2845084"},{"key":"e_1_3_2_1_47_1","volume-title":"A Modern Primer on Processing in Memory. arXiv preprint arXiv:2012.03112","author":"Mutlu Onur","year":"2020","unstructured":"Onur Mutlu , Saugata Ghose , Juan G\u00f3mez-Luna , and Rachata Ausavarungnirun . 2020. A Modern Primer on Processing in Memory. arXiv preprint arXiv:2012.03112 ( 2020 ). Onur Mutlu, Saugata Ghose, Juan G\u00f3mez-Luna, and Rachata Ausavarungnirun. 2020. A Modern Primer on Processing in Memory. arXiv preprint arXiv:2012.03112 (2020)."},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-10424-4_17"},{"key":"e_1_3_2_1_49_1","volume-title":"Proceedings. 25th Annual International Symposium on Computer Architecture.","author":"Oskin M.","unstructured":"M. Oskin , F. T. Chong , and T. Sherwood . 1998. Active Pages: a computation model for intelligent memory . In Proceedings. 25th Annual International Symposium on Computer Architecture. M. Oskin, F. T. Chong, and T. Sherwood. 1998. Active Pages: a computation model for intelligent memory. In Proceedings. 25th Annual International Symposium on Computer Architecture."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"crossref","unstructured":"D. Patterson T. Anderson N. Cardwell R. Fromm K. Keeton C. Kozyrakis R. Thomas and K. Yelick. 1997. A case for intelligent RAM. IEEE Micro (1997).  D. Patterson T. Anderson N. Cardwell R. Fromm K. Keeton C. Kozyrakis R. Thomas and K. Yelick. 1997. A case for intelligent RAM. IEEE Micro (1997).","DOI":"10.1109\/40.592312"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/2723372.2747645"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485278.2485284"},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169044"},{"key":"e_1_3_2_1_54_1","volume-title":"Readings in Artificial Intelligence and Databases","author":"Selinger P Griffiths","unstructured":"P Griffiths Selinger , Morton M Astrahan , Donald D Chamberlin , Raymond A Lorie , and Thomas G Price . 1989. Access path selection in a relational database management system . In Readings in Artificial Intelligence and Databases . Elsevier , 511--522. P Griffiths Selinger, Morton M Astrahan, Donald D Chamberlin, Raymond A Lorie, and Thomas G Price. 1989. Access path selection in a relational database management system. In Readings in Artificial Intelligence and Databases. Elsevier, 511--522."},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/3318464.3380595"},{"key":"e_1_3_2_1_56_1","unstructured":"Malcolm Singh and Ben Leonhardi. 2011. Introduction to the IBM Netezza warehouse appliance. In CASCON. IBM \/ ACM 385--386.  Malcolm Singh and Ben Leonhardi. 2011. Introduction to the IBM Netezza warehouse appliance. In CASCON. IBM \/ ACM 385--386."},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1970.5008902"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"crossref","unstructured":"Mike Stonebraker Daniel J Abadi Adam Batkin Xuedong Chen Mitch Cherniack Miguel Ferreira Edmond Lau Amerson Lin Sam Madden Elizabeth O'Neil etal 2018. C-store: a column-oriented DBMS. In Making Databases Work: the Pragmatic Wisdom of Michael Stonebraker. 491--518.  Mike Stonebraker Daniel J Abadi Adam Batkin Xuedong Chen Mitch Cherniack Miguel Ferreira Edmond Lau Amerson Lin Sam Madden Elizabeth O'Neil et al. 2018. C-store: a column-oriented DBMS. In Making Databases Work: the Pragmatic Wisdom of Michael Stonebraker. 491--518.","DOI":"10.1145\/3226595.3226638"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"crossref","unstructured":"Mike Stonebraker Daniel J Abadi Adam Batkin Xuedong Chen Mitch Cherniack Miguel Ferreira Edmond Lau Amerson Lin Sam Madden Elizabeth O'Neil etal 2018. C-store: a column-oriented DBMS. In Making Databases Work: the Pragmatic Wisdom of Michael Stonebraker. 491--518.  Mike Stonebraker Daniel J Abadi Adam Batkin Xuedong Chen Mitch Cherniack Miguel Ferreira Edmond Lau Amerson Lin Sam Madden Elizabeth O'Neil et al. 2018. C-store: a column-oriented DBMS. In Making Databases Work: the Pragmatic Wisdom of Michael Stonebraker. 491--518.","DOI":"10.1145\/3226595.3226638"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00035"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/3448016.3457260"},{"key":"e_1_3_2_1_62_1","volume-title":"The RISC-V Instruction Set Manual","author":"Waterman Andrew","unstructured":"Andrew Waterman , Yunsup Lee , David A. Patterson , and Krste Asanovic . 2014. The RISC-V Instruction Set Manual . Volume I User-level ISA. https:\/\/www.amd.com\/en\/products\/cpu\/amd-epyc-7502. Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanovic. 2014. The RISC-V Instruction Set Manual. Volume I User-level ISA. https:\/\/www.amd.com\/en\/products\/cpu\/amd-epyc-7502."},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1145\/362084.362137"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.51"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00041"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"crossref","unstructured":"L. Yavits A. Morad and R. Ginosar. 2015. Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. IEEE Trans. Comput. (2015).  L. Yavits A. Morad and R. Ginosar. 2015. Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. IEEE Trans. Comput. (2015).","DOI":"10.1109\/TC.2013.220"},{"key":"e_1_3_2_1_67_1","volume-title":"Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors.","author":"Kang Yi","unstructured":"Yi Kang , Wei Huang , Seung-Moon Yoo , D. Keen , Zhenzhou Ge , V. Lam , P. Pattnaik , and J. Torrellas . 1999. FlexRAM: toward an advanced intelligent memory system . In Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors. Yi Kang, Wei Huang, Seung-Moon Yoo, D. Keen, Zhenzhou Ge, V. Lam, P. Pattnaik, and J. Torrellas. 1999. FlexRAM: toward an advanced intelligent memory system. In Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors."},{"key":"e_1_3_2_1_68_1","volume-title":"Hyper-AP: Enhancing Associative Processing Through A Full-Stack Optimization. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture.","author":"Zha Y.","unstructured":"Y. Zha and J. Li . 2020 . Hyper-AP: Enhancing Associative Processing Through A Full-Stack Optimization. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture. Y. Zha and J. Li. 2020. Hyper-AP: Enhancing Associative Processing Through A Full-Stack Optimization. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture."},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/564691.564709"}],"event":{"name":"ISCA '22: The 49th Annual International Symposium on Computer Architecture","location":"New York New York","acronym":"ISCA '22","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE CS TCAA IEEE CS technical committee on architectural acoustics"]},"container-title":["Proceedings of the 49th Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3470496.3527435","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3470496.3527435","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:18:54Z","timestamp":1750191534000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3470496.3527435"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,11]]},"references-count":69,"alternative-id":["10.1145\/3470496.3527435","10.1145\/3470496"],"URL":"https:\/\/doi.org\/10.1145\/3470496.3527435","relation":{},"subject":[],"published":{"date-parts":[[2022,6,11]]},"assertion":[{"value":"2022-06-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}