{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T15:49:45Z","timestamp":1781884185204,"version":"3.54.5"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2021,9,27]],"date-time":"2021-09-27T00:00:00Z","timestamp":1632700800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001659","name":"German Research Foundation","doi-asserted-by":"crossref","award":["PI 447\/8 and GA 763\/7"],"award-info":[{"award-number":["PI 447\/8 and GA 763\/7"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Model. Comput. Simul."],"published-print":{"date-parts":[[2022,1,31]]},"abstract":"<jats:p>\n            We introduce\n            <jats:italic>Ratatoskr<\/jats:italic>\n            , an open-source framework for in-depth power, performance, and area (PPA) analysis in Networks-on-Chips (NoCs) for 3D-integrated and heterogeneous System-on-Chips (SoCs). It covers all layers of abstraction by providing an NoC hardware implementation on Register Transfer Level (RTL), an NoC simulator on cycle-accurate level and an application model on transaction level. By this comprehensive approach,\n            <jats:italic>Ratatoskr<\/jats:italic>\n            can provide the following specific PPA analyses: Dynamic power of links can be measured within 2.4% accuracy of bit-level simulations while maintaining cycle-accurate simulation speed. Router power is determined from RTL-to-gate-level synthesis combined with cycle-accurate simulations. The performance of the whole NoC can be measured both via cycle-accurate and RTL simulations. The performance (i.e., timing) of individual routers and the NoC area are obtained from RTL synthesis results. Despite these manifold features,\n            <jats:italic>Ratatoskr<\/jats:italic>\n            offers easy two-step user interaction: (1) A single point-of-entry allows setting design parameters. (2) PPA reports are generated automatically. For both the input and the output, different levels of abstraction can be chosen for high-level rapid network analysis or low-level improvement of architectural details. The synthesizable NoC-RTL model shows improved total router power and area in comparison to a conventional standard router. As a forward-thinking and unique feature not found in other NoC PPA-measurement tools,\n            <jats:italic>Ratatoskr<\/jats:italic>\n            supports heterogeneous 3D integration that is one of the most promising integration paradigms for upcoming SoCs. Thereby,\n            <jats:italic>Ratatoskr<\/jats:italic>\n            lays the groundwork to design their communication architectures. The framework is publicly available at\n            <jats:underline>\n              <jats:ext-link xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" ext-link-type=\"url\" xlink:href=\"https:\/\/github.com\/ratatoskr-project\">https:\/\/github.com\/ratatoskr-project<\/jats:ext-link>\n            <\/jats:underline>\n            .\n          <\/jats:p>","DOI":"10.1145\/3472754","type":"journal-article","created":{"date-parts":[[2021,9,28]],"date-time":"2021-09-28T04:37:09Z","timestamp":1632803829000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs"],"prefix":"10.1145","volume":"32","author":[{"given":"Jan Moritz","family":"Joseph","sequence":"first","affiliation":[{"name":"RWTH Aachen University, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lennart","family":"Bamberg","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Bremen, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Imad","family":"Hajjar","sequence":"additional","affiliation":[{"name":"Otto von Guericke Universit\u00e4t Magdeburg, Magdeburg, Sachsen-Anhalt, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Behnam Razi","family":"Perjikolaei","sequence":"additional","affiliation":[{"name":"OFFIS\u2014Institut f\u00fcr Informatik, Oldenburg, Niedersachsen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alberto","family":"Garc\u00eda-Ortiz","sequence":"additional","affiliation":[{"name":"Universit\u00e4t Bremen, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Thilo","family":"Pionteck","sequence":"additional","affiliation":[{"name":"Otto von Guericke Universit\u00e4t Magdeburg, Magdeburg, Sachsen-Anhalt, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2021,9,27]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software. IEEE, 33\u201342","author":"Agarwal Niket","unstructured":"Niket Agarwal , Tushar Krishna , Li-Shiuan Peh , and Niraj K. Jha . 2009. GARNET: A detailed on-chip network model inside a full-system simulator . In Proceedings of the International Symposium on Performance Analysis of Systems and Software. IEEE, 33\u201342 . Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, and Niraj K. Jha. 2009. GARNET: A detailed on-chip network model inside a full-system simulator. In Proceedings of the International Symposium on Performance Analysis of Systems and Software. IEEE, 33\u201342."},{"key":"e_1_2_1_2_1","volume-title":"Retrieved","year":"2014","unstructured":"anan-cn. 2014 . Open-Source Network-on-Chip Router RTL . Retrieved March 15, 2019 from https:\/\/github.com\/anan-cn\/Open-Source-Network-on-Chip-Router-RTL. anan-cn. 2014. Open-Source Network-on-Chip Router RTL. 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Efficient Microarchitecture for Network-on-Chip Routers. Stanford University, Stanford, CA."},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/1654059.1654112"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2953878"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"e_1_2_1_14_1","volume-title":"Retrieved","author":"Fatollahi-Fard Farzad","year":"2019","unstructured":"Farzad Fatollahi-Fard , David Donofrio , George Michelogiannakis , Ke Shalf , John adn Wen , John Bachan , and Daniel Burke . 2019 . OpenSoCFabric . Retrieved March 15, 2019 from http:\/\/www.opensocfabric.org\/home.php. Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, Ke Shalf, John adn Wen, John Bachan, and Daniel Burke. 2019. OpenSoCFabric. Retrieved March 15, 2019 from http:\/\/www.opensocfabric.org\/home.php."},{"key":"e_1_2_1_15_1","volume-title":"Noxim: Network-on-Chip Simulator. https:\/\/github.com\/davidepatti\/noxim.","author":"Fazzino Fabrizio","year":"2008","unstructured":"Fabrizio Fazzino , Maurizio Palesi , and David Patti . 2008 . Noxim: Network-on-Chip Simulator. https:\/\/github.com\/davidepatti\/noxim. Fabrizio Fazzino, Maurizio Palesi, and David Patti. 2008. Noxim: Network-on-Chip Simulator. https:\/\/github.com\/davidepatti\/noxim."},{"key":"e_1_2_1_16_1","volume-title":"Handbook of 3D Integration (1st. ed.).","author":"Garrou P. E.","unstructured":"P. E. Garrou , M. Koyanagi , and P. Ramm( Eds .). 2009. 3D process technology: Robust circuit and physical design for sub-65 nm technology nodes . In Handbook of 3D Integration (1st. ed.). Vol. 3 , Wiley , Hoboken, NJ . P. E. Garrou, M. Koyanagi, and P. Ramm(Eds.). 2009. 3D process technology: Robust circuit and physical design for sub-65 nm technology nodes. In Handbook of 3D Integration (1st. ed.). Vol. 3, Wiley, Hoboken, NJ."},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"e_1_2_1_18_1","volume-title":"Booksim Interconnection Network Simulator. Retrieved","author":"Jiang N.","year":"2021","unstructured":"N. Jiang , G. Michelogiannakis , D. Becker , B. Towles , and W. Dally . 2017 . Booksim Interconnection Network Simulator. Retrieved July 02, 2021 from https:\/\/github.com\/booksim\/booksim2. N. Jiang, G. Michelogiannakis, D. Becker, B. Towles, and W. Dally. 2017. Booksim Interconnection Network Simulator. Retrieved July 02, 2021 from https:\/\/github.com\/booksim\/booksim2."},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2942129"},{"key":"e_1_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2019.05.005"},{"key":"e_1_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2018.8449387"},{"key":"e_1_2_1_22_1","volume-title":"Proceedings of the International Symposium on System-on-Chip. IEEE, 1\u20136. DOI:https:\/\/doi.org\/10","author":"Pionteck J.","year":"2014","unstructured":"Joseph, J. M. and T. Pionteck . 2014. A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling . In Proceedings of the International Symposium on System-on-Chip. IEEE, 1\u20136. DOI:https:\/\/doi.org\/10 .1109\/ISSOC. 2014 .6972440 10.1109\/ISSOC.2014.6972440 Joseph, J. M. and T. Pionteck. 2014. A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling. In Proceedings of the International Symposium on System-on-Chip. IEEE, 1\u20136. DOI:https:\/\/doi.org\/10.1109\/ISSOC.2014.6972440"},{"key":"e_1_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.5555\/1874620.1874721"},{"key":"e_1_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2015.2402197"},{"key":"e_1_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2034508"},{"key":"e_1_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007157"},{"key":"e_1_2_1_27_1","volume-title":"OpenSMART. Retrieved","year":"2019","unstructured":"Krishna. Krishna and Hyoukjun Kwon. 2017 . OpenSMART. Retrieved March 15, 2019 from http:\/\/synergy.ece.gatech.edu\/tools\/opensmart\/. Krishna. Krishna and Hyoukjun Kwon. 2017. OpenSMART. Retrieved March 15, 2019 from http:\/\/synergy.ece.gatech.edu\/tools\/opensmart\/."},{"key":"e_1_2_1_28_1","volume-title":"Proceedings of the International Symposium on Performance Analysis of Systems and Software. IEEE, 195\u2013204","author":"Kwon H.","year":"2017","unstructured":"H. Kwon and T. Krishna . 2017. OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel . In Proceedings of the International Symposium on Performance Analysis of Systems and Software. IEEE, 195\u2013204 . DOI:https:\/\/doi.org\/10.1109\/ISPASS. 2017 .7975291 10.1109\/ISPASS.2017.7975291 H. Kwon and T. Krishna. 2017. OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel. In Proceedings of the International Symposium on Performance Analysis of Systems and Software. IEEE, 195\u2013204. DOI:https:\/\/doi.org\/10.1109\/ISPASS.2017.7975291"},{"key":"e_1_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.386219"},{"key":"e_1_2_1_30_1","volume-title":"The Next Generation AMD Enterprise Server Product Architecture. Retrieved","author":"Lepak K.","year":"2021","unstructured":"K. Lepak , G. Talbot , S. White , N. Beck , and S. Naffziger . 2017 . The Next Generation AMD Enterprise Server Product Architecture. Retrieved July 24, 2021 from https:\/\/old.hotchips.org\/. K. Lepak, G. Talbot, S. White, N. Beck, and S. Naffziger. 2017. The Next Generation AMD Enterprise Server Product Architecture. Retrieved July 24, 2021 from https:\/\/old.hotchips.org\/."},{"key":"e_1_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2006.9"},{"key":"e_1_2_1_32_1","volume-title":"Retrieved","author":"Intel","year":"2019","unstructured":"Intel PR. 2019 . Intel Previews New Hybrid CPU Architecture with Foveros 3D Packaging . Retrieved May 17, 2019 from https:\/\/newsroom.intel.com\/video-archive\/video-intel-previews-new-hybrid-cpu-architecture-with-foveros-3d-packaging\/. Intel PR. 2019. Intel Previews New Hybrid CPU Architecture with Foveros 3D Packaging. Retrieved May 17, 2019 from https:\/\/newsroom.intel.com\/video-archive\/video-intel-previews-new-hybrid-cpu-architecture-with-foveros-3d-packaging\/."},{"key":"e_1_2_1_33_1","volume-title":"SPICE. Retrieved","author":"Quarles T.","year":"2020","unstructured":"T. Quarles , D. Pederson , R. Newton , A. Sangiovanni-Vincentelli , and C. Wayne . 2020 . SPICE. Retrieved October 14, 2020 from http:\/\/bwrcs.eecs.berkeley.edu\/Classes\/IcBook\/SPICE\/. T. Quarles, D. Pederson, R. Newton, A. Sangiovanni-Vincentelli, and C. Wayne. 2020. SPICE. Retrieved October 14, 2020 from http:\/\/bwrcs.eecs.berkeley.edu\/Classes\/IcBook\/SPICE\/."},{"key":"e_1_2_1_34_1","unstructured":"tgingold.2020. GHDL. Retrieved October 14 2020 from https:\/\/github.com\/ghdl\/ghdl.  tgingold.2020. GHDL. Retrieved October 14 2020 from https:\/\/github.com\/ghdl\/ghdl."},{"key":"e_1_2_1_35_1","volume-title":"Retrieved","year":"2020","unstructured":"tgingold.2020. ghdl-yosys-plugin : VHDL synthesis . Retrieved October 14, 2020 from https:\/\/github.com\/ghdl\/ghdl-yosys-plugin. tgingold.2020. ghdl-yosys-plugin: VHDL synthesis. Retrieved October 14, 2020 from https:\/\/github.com\/ghdl\/ghdl-yosys-plugin."},{"key":"e_1_2_1_36_1","volume-title":"Retrieved","author":"Wolf Claire","year":"2020","unstructured":"Claire Wolf . 2020 . Yosys open synthesis suite . Retrieved October 14, 2020 from http:\/\/www.clifford.at\/yosys\/about.html. Claire Wolf. 2020. Yosys open synthesis suite. Retrieved October 14, 2020 from http:\/\/www.clifford.at\/yosys\/about.html."},{"key":"e_1_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCA.2013.6565107"},{"key":"e_1_2_1_38_1","volume-title":"Focal-Plane Sensor-Processor Chips","author":"Zar\u00e1ndy \u00c1kos","unstructured":"\u00c1kos Zar\u00e1ndy . 2011. Focal-Plane Sensor-Processor Chips . Springer , New York, NY . \u00c1kos Zar\u00e1ndy. 2011. Focal-Plane Sensor-Processor Chips. Springer, New York, NY."}],"container-title":["ACM Transactions on Modeling and Computer Simulation"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3472754","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3472754","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:17:09Z","timestamp":1750191429000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3472754"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,27]]},"references-count":37,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2022,1,31]]}},"alternative-id":["10.1145\/3472754"],"URL":"https:\/\/doi.org\/10.1145\/3472754","relation":{},"ISSN":["1049-3301","1558-1195"],"issn-type":[{"value":"1049-3301","type":"print"},{"value":"1558-1195","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,9,27]]},"assertion":[{"value":"2020-01-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-06-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-09-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}