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Syst."],"published-print":{"date-parts":[[2022,4,30]]},"abstract":"<jats:p>\n            In this article, we propose a hardware accelerator design using\n            <jats:bold>ferroelectric transistor (FeFET)-based hybrid precision synapse (HPS)<\/jats:bold>\n            for\n            <jats:bold>deep neural network (DNN)<\/jats:bold>\n            on-chip training. The drain erase scheme for FeFET programming is incorporated for both FeFET HPS design and FeFET buffer design. By using drain erase, high-density FeFET buffers can be integrated onchip to store the intermediate input-output activations and gradients, which reduces the energy consuming off-chip DRAM access. Architectural evaluation results show that the energy efficiency could be improved by 1.2\u00d7 \u223c 2.1\u00d7, 3.9\u00d7 \u223c 6.0\u00d7 compared to the other HPS-based designs and emerging non-volatile memory baselines, respectively. The chip area is reduced by 19% \u223c 36% compared with designs using SRAM on-chip buffer even though the capacity of FeFET buffer is increased. Besides, by utilizing drain erase scheme for FeFET programming, the chip area is reduced by 11% \u223c 28.5% compared with the designs using body erase scheme.\n          <\/jats:p>","DOI":"10.1145\/3473461","type":"journal-article","created":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T14:06:38Z","timestamp":1641996398000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8239-0492","authenticated-orcid":false,"given":"Yandong","family":"Luo","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Panni","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,1,12]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"388","volume-title":"2019 IEEE International Solid-State Circuits Conference (ISSCC\u201919)","author":"Xue Cheng-Xin","year":"2019","unstructured":"Cheng-Xin Xue et al. 2019. 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