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Syst."],"published-print":{"date-parts":[[2021,10,31]]},"abstract":"<jats:p>\n            <jats:italic>Intermittent systems<\/jats:italic>\n            enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In particular, a\n            <jats:italic>delegable<\/jats:italic>\n            and\n            <jats:italic>adaptive synchronization<\/jats:italic>\n            protocol is proposed to allow memory accesses to be delegated between cores and to dynamically adapt to diverse memory access latency. Moreover, our design guarantees\n            <jats:italic>task serializability<\/jats:italic>\n            across multiple cores and maintains\n            <jats:italic>data consistency<\/jats:italic>\n            despite frequent power failures. We integrated our design into FreeRTOS running on a Cypress device featuring heterogeneous dual cores and hybrid memories. Experimental results show that, compared to recent approaches that assume single-core intermittent systems, our design can improve computation progress at least 1.8x and even up to 33.9x by leveraging core heterogeneity.\n          <\/jats:p>","DOI":"10.1145\/3476992","type":"journal-article","created":{"date-parts":[[2021,9,17]],"date-time":"2021-09-17T18:36:51Z","timestamp":1631903811000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["Heterogeneity-aware Multicore Synchronization for Intermittent Systems"],"prefix":"10.1145","volume":"20","author":[{"given":"Wei-Ming","family":"Chen","sequence":"first","affiliation":[{"name":"Academia Sinica and National Taiwan University, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tei-Wei","family":"Kuo","sequence":"additional","affiliation":[{"name":"City University of Hong Kong, China and National Taiwan University, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pi-Cheng","family":"Hsiu","sequence":"additional","affiliation":[{"name":"Academia Sinica, National Taiwan University and National Chi Nan University, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,9,17]]},"reference":[{"unstructured":"n.d. A Heterogeneity-aware Multicore Intermittent Operating System. Available: https:\/\/github.com\/EMCLab-Sinica\/Intermittent-Multicore.  n.d. A Heterogeneity-aware Multicore Intermittent Operating System. Available: https:\/\/github.com\/EMCLab-Sinica\/Intermittent-Multicore.","key":"e_1_2_1_1_1"},{"unstructured":"n.d. An Intermittent Operating System. Available: https:\/\/github.com\/EMCLab-Sinica\/Intermittent-OS.  n.d. An Intermittent Operating System. Available: https:\/\/github.com\/EMCLab-Sinica\/Intermittent-OS.","key":"e_1_2_1_2_1"},{"unstructured":"n.d. The FreeRTOS\u2122 Kernel. Available: https:\/\/www.freertos.org.  n.d. The FreeRTOS\u2122 Kernel. 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