{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:17:35Z","timestamp":1750220255951,"version":"3.41.0"},"reference-count":47,"publisher":"Association for Computing Machinery (ACM)","issue":"5s","license":[{"start":{"date-parts":[[2021,9,22]],"date-time":"2021-09-22T00:00:00Z","timestamp":1632268800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2021,10,31]]},"abstract":"<jats:p>Modern computer server systems are increasingly managed at a low level by baseboard management controllers (BMCs). BMCs are processors with access to the most critical parts of the platform, below the level of OS or hypervisor, including control over power delivery to every system component. Buggy or poorly designed BMC software not only poses a security threat to a machine, it can permanently render the hardware inoperative. Despite this, there is little published work on how to rigorously engineer the power management functionality of BMCs so as to prevent this happening.<\/jats:p>\n          <jats:p>This article takes a first step toward putting BMC software on a sound footing by specifying the hardware environment and the constraints necessary for safe and correct operation. This is best accomplished through automation: correct-by-construction power control sequences can be efficiently generated from a simple, trustworthy model of the platform\u2019s power tree that incorporates the sequencing requirements and safe voltage ranges of all components.<\/jats:p>\n          <jats:p>We present both a modeling language for complex power-delivery networks and a tool to automatically generate safe, efficient power sequences for complex modern platforms. This not only increases the trustworthiness of a hitherto opaque yet critical element of platform firmware: regulator and chip power models are significantly simpler to produce than hand-written power sequences. This, combined with model reuse for common components, reduces both time and cost associated with platform bring-up for new hardware.<\/jats:p>\n          <jats:p>We evaluate our tool using a new high-performance 2-socket server platform with &gt;100W per socket TDP, tight voltage limits and 25 distinct power regulators needing configuration, showing both fast (&lt;10s) tool runtime, and correct power sequencing of a live system.<\/jats:p>","DOI":"10.1145\/3477039","type":"journal-article","created":{"date-parts":[[2021,9,22]],"date-time":"2021-09-22T20:48:40Z","timestamp":1632343720000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Declarative Power Sequencing"],"prefix":"10.1145","volume":"20","author":[{"given":"Jasmin","family":"Schult","sequence":"first","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Schwyn","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Giardino","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Cock","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Reto","family":"Achermann","sequence":"additional","affiliation":[{"name":"University of British Columbia, Vancouver, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timothy","family":"Roscoe","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,9,22]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2380356.2380398"},{"key":"e_1_2_1_2_1","volume-title":"10th Conference on Innovative Data Systems Research, CIDR","author":"Alonso Gustavo","year":"2020","unstructured":"Gustavo Alonso , Timothy Roscoe , David Cock , Mohsen Ewaida , Kaan Kara , Dario Korolija , David Sidler , and Zeke Wang . 2020. Tackling Hardware\/Software co-design from a database perspective. In 10th Conference on Innovative Data Systems Research, CIDR 2020 , Amsterdam, The Netherlands , January 12-15, 2020, Online Proceedings. CIDR , www.cidrdb.org, 6 pages. http:\/\/cidrdb.org\/cidr2020\/papers\/p30-alonso-cidr20.pdf. Gustavo Alonso, Timothy Roscoe, David Cock, Mohsen Ewaida, Kaan Kara, Dario Korolija, David Sidler, and Zeke Wang. 2020. Tackling Hardware\/Software co-design from a database perspective. In 10th Conference on Innovative Data Systems Research, CIDR 2020, Amsterdam, The Netherlands, January 12-15, 2020, Online Proceedings. CIDR, www.cidrdb.org, 6 pages. http:\/\/cidrdb.org\/cidr2020\/papers\/p30-alonso-cidr20.pdf."},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/92.845896"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/2534748.2534761"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2873584"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/502059.502042"},{"key":"e_1_2_1_7_1","unstructured":"Altera Corporation. 2014. Enpirion Power Datasheet ES1020QI Power Sequencing Controller. https:\/\/eu.mouser.com\/datasheet\/2\/612\/es1020qi_10041-1299392.pdf.  Altera Corporation. 2014. Enpirion Power Datasheet ES1020QI Power Sequencing Controller. https:\/\/eu.mouser.com\/datasheet\/2\/612\/es1020qi_10041-1299392.pdf."},{"key":"e_1_2_1_8_1","unstructured":"CVE. 2019. CVE-2019-4169.Available from MITRE CVE-ID CVE-2019-4169. http:\/\/cve.mitre.org\/cgi-bin\/cvename.cgi?name=CVE-2019-4169.  CVE. 2019. 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