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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2022,1,31]]},"abstract":"<jats:p>\n            Brain network is a large-scale complex network with scale-free, small-world, and modularity properties, which largely supports this high-efficiency massive system. In this article, we propose to synthesize brain-network-inspired interconnections for large-scale network-on-chips. First, we propose a method to generate brain-network-inspired topologies with limited scale-free and power-law small-world properties, which have a low total link length and extremely low average hop count approximately proportional to the logarithm of the network size. In addition, given the large-scale applications, considering the modularity of the brain-network-inspired topologies, we present an application mapping method, including task mapping and deterministic deadlock-free routing, to minimize the power consumption and hop count. Finally, a cycle-accurate simulator\n            <jats:inline-formula content-type=\"math\/tex\">\n              <jats:tex-math notation=\"TeX\" version=\"MathJax\">BookSim2<\/jats:tex-math>\n            <\/jats:inline-formula>\n            is used to validate the architecture performance with different synthetic traffic patterns and large-scale test cases, including real-world communication networks for the graph processing application. Experiments show that, compared with other topologies and methods, the brain-network-inspired network-on-chips (NoCs) generated by the proposed method present significantly lower average hop count and lower average latency. Especially in graph processing applications with a power-law and tightly coupled inter-core communication, the brain-network-inspired NoC has up to 70% lower average hop count and 75% lower average latency than mesh-based NoCs.\n          <\/jats:p>","DOI":"10.1145\/3480961","type":"journal-article","created":{"date-parts":[[2021,10,16]],"date-time":"2021-10-16T00:33:40Z","timestamp":1634344420000},"page":"1-30","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips"],"prefix":"10.1145","volume":"27","author":[{"given":"Mengke","family":"Ge","sequence":"first","affiliation":[{"name":"School of Microelectronics, University of Science and Technology of China (USTC), Hefei, Anhui, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaobing","family":"Ni","sequence":"additional","affiliation":[{"name":"School of Microelectronics, University of Science and Technology of China (USTC), Hefei, Anhui, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xu","family":"Qi","sequence":"additional","affiliation":[{"name":"School of Microelectronics, University of Science and Technology of China (USTC), Hefei, Anhui, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Song","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Microelectronics, USTC, and Institute of Artificial Intelligence, Hefei Comprehensive National Science Center, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinglei","family":"Huang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Air Traffic Management System and Technology, Nanjing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi","family":"Kang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, USTC, and Institute of Artificial Intelligence, Hefei Comprehensive National Science Center, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Feng","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, USTC, and Institute of Artificial Intelligence, Hefei Comprehensive National Science Center, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2021,10,15]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"ITRS. 2007. International Technology Roadmap for Semiconductors. Retrieved from http:\/\/www.itrs.net.  ITRS. 2007. International Technology Roadmap for Semiconductors. Retrieved from http:\/\/www.itrs.net."},{"key":"e_1_2_1_2_1","first-page":"17","article-title":"Communication dynamics in complex brain networks","volume":"19","author":"Andrea A.","year":"2017","unstructured":"A. Andrea , M. Bratislav , and S. Olaf . 2017 . Communication dynamics in complex brain networks . Nature Rev. Neurosci. 19 (2017), 17 \u2013 33 . A. Andrea, M. Bratislav, and S. Olaf.2017. Communication dynamics in complex brain networks. Nature Rev. Neurosci. 19 (2017), 17\u201333.","journal-title":"Nature Rev. Neurosci."},{"key":"e_1_2_1_3_1","volume-title":"Proceedings of the 29th IEEE International System-on-Chip Conference (SOCC\u201916)","author":"Bai M.","unstructured":"M. Bai , D. Zhao , and H. Wu . 2016. CATBR-congestion aware traffic bridging routing among hierarchical networks-on-chip . In Proceedings of the 29th IEEE International System-on-Chip Conference (SOCC\u201916) . 52\u201357. M. Bai, D. Zhao, and H. Wu. 2016. CATBR-congestion aware traffic bridging routing among hierarchical networks-on-chip. In Proceedings of the 29th IEEE International System-on-Chip Conference (SOCC\u201916). 52\u201357."},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"e_1_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1126\/science.286.5439.509"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2313565"},{"key":"e_1_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"key":"e_1_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1088\/1742-5468\/2008\/10\/P10008"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/1278480.1278667"},{"key":"e_1_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.105"},{"key":"e_1_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2012.289"},{"key":"e_1_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2952134"},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.5555\/995703"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2604288"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2013.130602"},{"key":"e_1_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.94.018102"},{"key":"e_1_2_1_17_1","volume-title":"2014. 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Spatial small-world networks: A wiring-cost perspective. arXiv e-prints (2005). arXiv:cond-mat\/0501420."},{"key":"e_1_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/2517349.2522740"},{"key":"e_1_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2012.10.004"},{"key":"e_1_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2588555.2610518"},{"key":"e_1_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.5555\/3014904.3014920"},{"key":"e_1_2_1_49_1","unstructured":"K. Simonyan and A. Zisserman. 2014. Very deep convolutional networks for large-scale image recognition. Retrieved from https:\/\/arxiv:1409.1556.  K. Simonyan and A. Zisserman. 2014. Very deep convolutional networks for large-scale image recognition. Retrieved from https:\/\/arxiv:1409.1556."},{"key":"e_1_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1146\/annurev-psych-122414-033634"},{"key":"e_1_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2003.813040"},{"key":"e_1_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1063\/1.2740566"},{"key":"e_1_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2413848"},{"key":"e_1_2_1_54_1","volume-title":"Proceedings of the International Conference on Application of Information and Communication Technologies. 1\u20135. https:\/\/doi.org\/10","author":"Tosun S.","year":"2009","unstructured":"S. Tosun , O. Ozturk , and M. Ozen . 2009. An ILP formulation for application mapping onto Network-on-Chips . In Proceedings of the International Conference on Application of Information and Communication Technologies. 1\u20135. https:\/\/doi.org\/10 .1109\/ICAICT. 2009 .5372524 10.1109\/ICAICT.2009.5372524 S. Tosun, O. Ozturk, and M. Ozen. 2009. An ILP formulation for application mapping onto Network-on-Chips. In Proceedings of the International Conference on Application of Information and Communication Technologies. 1\u20135. https:\/\/doi.org\/10.1109\/ICAICT.2009.5372524"},{"key":"e_1_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.tics.2013.09.012"},{"key":"e_1_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1587\/elex.15.20180738"},{"key":"e_1_2_1_57_1","doi-asserted-by":"crossref","unstructured":"D. J. Watts and S. H. Strogatz. 1998. Collective dynamics of small world networks. Nature 393 6684 (1998) 440\u2013442.  D. J. Watts and S. H. Strogatz. 1998. Collective dynamics of small world networks. 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