{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:18:45Z","timestamp":1750220325776,"version":"3.41.0"},"reference-count":110,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2021,11,2]],"date-time":"2021-11-02T00:00:00Z","timestamp":1635811200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"ReAp: Runtime Reconfigurable Approximate Architecture","award":["380524764"],"award-info":[{"award-number":["380524764"]}]},{"name":"German research foundation Deutsche Forschungsgemeinschaft (DFG) and Re-learning: Self-learning and flexible electronics through inherent component reconfiguration","award":["100382146"],"award-info":[{"award-number":["100382146"]}]},{"DOI":"10.13039\/501100004895","name":"European Social Fund","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100004895","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2022,3,31]]},"abstract":"<jats:p>\n            The rapid evolution of error-resilient programs intertwined with their quest for high throughput has motivated the use of Single Instruction, Multiple Data (SIMD) components in Field-Programmable Gate Arrays (FPGAs). Particularly, to exploit the error-resiliency of such applications,\n            <jats:italic>Cross-layer<\/jats:italic>\n            approximation paradigm has recently gained traction, the ultimate goal of which is to efficiently exploit approximation potentials across layers of abstraction. From circuit- to application-level, valuable studies have proposed various approximation techniques, albeit linked to four drawbacks: First, most of approximate multipliers and dividers operate only in SISD mode. Second, imprecise units are often substituted, merely in a single kernel of a multi-kernel application, with an\n            <jats:italic>end-to-end<\/jats:italic>\n            analysis in Quality of Results (QoR) and not in the gained performance. Third, state-of-the-art (SoA) strategies neglect the fact that each kernel contributes differently to the end-to-end QoR and performance metrics. Therefore, they lack in adopting a generic methodology for adjusting the approximation knobs to maximize performance gains for a user-defined quality constraint. Finally, multi-level techniques lack in being efficiently supported, from application-, to architecture-, to circuit-level, in a cohesive cross-layer hierarchy.\n          <\/jats:p>\n          <jats:p>\n            In this article, we propose\n            <jats:italic>Plasticine<\/jats:italic>\n            , a cross-layer methodology for multi-kernel applications, which addresses the aforementioned challenges by efficiently utilizing the synergistic effects of a chain of techniques across layers of abstraction. To this end, we propose an application sensitivity analysis and a heuristic that tailor the precision at constituent kernels of the application by finding the most tolerable degree of approximations for each of consecutive kernels, while also satisfying the ultimate user-defined QoR. The chain of approximations is also effectively enabled in a cross-layer hierarchy, from application- to architecture- to circuit-level, through the plasticity of SIMD multiplier-dividers, each supporting dynamic precision variability along with hybrid functionality. The end-to-end evaluations of Plasticine\u00a0 on three multi-kernel applications employed in bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) demonstrate 41%\u201364%, 39%\u201362%, and 70%\u201386% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over 32-bit fixed precision, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and open-sourced at https:\/\/cfaed.tu-dresden.de\/pd-downloads.\n          <\/jats:p>","DOI":"10.1145\/3486616","type":"journal-article","created":{"date-parts":[[2021,11,2]],"date-time":"2021-11-02T20:19:32Z","timestamp":1635884372000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider"],"prefix":"10.1145","volume":"27","author":[{"given":"Zahra","family":"Ebrahimi","sequence":"first","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Saxony, Germany"}]},{"given":"Dennis","family":"Klar","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Saxony, Germany"}]},{"given":"Mohammad Aasim","family":"Ekhtiyar","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Saxony, Germany"}]},{"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[{"name":"Technische Universit\u00e4t Dresden, Dresden, Saxony, Germany"}]}],"member":"320","published-online":{"date-parts":[[2021,11,2]]},"reference":[{"key":"e_1_3_2_2_2","article-title":"Cardiovascular diseases (CVDs)","author":"Organisation World Health","year":"2018","unstructured":"World Health Organisation. 2018. Cardiovascular diseases (CVDs). Retrieved from https:\/\/www.who.int\/news-room\/fact-sheets\/detail\/cardiovascular-diseases-(cvds).","journal-title":"Retrieved from https:\/\/www.who.int\/news-room\/fact-sheets\/detail\/cardiovascular-diseases-(cvds)"},{"key":"e_1_3_2_3_2","article-title":"Heart Disease and Early Heart Attack Care","author":"Kostic P.","year":"2017","unstructured":"P. Kostic. 2017. Heart Disease and Early Heart Attack Care. Retrieved from https:\/\/www.bnl.gov\/hr\/occmed\/hpp\/linkable_files\/pdf\/EarlyHeartAttackSymptoms.pdf.","journal-title":"Retrieved from https:\/\/www.bnl.gov\/hr\/occmed\/hpp\/linkable_files\/pdf\/EarlyHeartAttackSymptoms.pdf"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00077"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/2821508"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1504\/IJBET.2015.068112"},{"key":"e_1_3_2_7_2","volume-title":"IEEE Trans. Comput.-aided Des. Integ. Circ. Syst.","author":"Ullah S.","year":"2021","unstructured":"S. Ullah, S. Rehman, M. Shafique, and A. Kumar. 2021. High-performance accurate and approximate multipliers for FPGA-based hardware accelerators. IEEE Trans. Comput.-aided Des. Integ. Circ. Syst. (2021)."},{"key":"e_1_3_2_8_2","volume-title":"IEEE\/ACM Design Automation Conference (DAC)","author":"Ullah S.","year":"2018","unstructured":"S. Ullah, S. Rehman, B. S. Prabakaran, F. Kriebel, M. A. Hanif, M. Shafique, and A. Kumar. 2018. Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators. In IEEE\/ACM Design Automation Conference (DAC)."},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00014"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2824280"},{"key":"e_1_3_2_12_2","article-title":"LogiCORE IP multiplier v12.0","year":"2015","unstructured":"Xilinx. 2015. LogiCORE IP multiplier v12.0. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/mult_gen\/v12_0\/pg108-mult-gen.pdf.","journal-title":"Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/mult_gen\/v12_0\/pg108-mult-gen.pdf"},{"key":"e_1_3_2_13_2","article-title":"LogiCORE IP Divider v5.1","year":"2016","unstructured":"Xilinx. 2016. LogiCORE IP Divider v5.1. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/div_gen\/v5_1\/pg151-div-gen.pdf.","journal-title":"Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/div_gen\/v5_1\/pg151-div-gen.pdf"},{"key":"e_1_3_2_14_2","article-title":"7 Series DSP48E1 Slice","year":"2018","unstructured":"Xilinx. 2018. 7 Series DSP48E1 Slice. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug479_7Series_DSP48E1.pdf.","journal-title":"Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug479_7Series_DSP48E1.pdf"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2970968"},{"key":"e_1_3_2_16_2","volume-title":"ACM Great Lakes Symposium on VLSI (GLSVLSI)","author":"Ebrahimi Z.","year":"2020","unstructured":"Z. Ebrahimi, S. Ullah, and A. Kumar. 2020. SIMDive: Approximate SIMD Soft multiplier-divider for FPGAs with tunable accuracy. In ACM Great Lakes Symposium on VLSI (GLSVLSI)."},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317773"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2857262"},{"key":"e_1_3_2_19_2","volume-title":"International Conference on Supercomputing (ICS)","author":"Judd P.","year":"2016","unstructured":"P. Judd, J. Albericio, T. Hetherington, T. Aamodt, N. E. Jerger, and A. Moshovos. 2016. Proteus: Exploiting numerical precision variability in deep neural networks. In International Conference on Supercomputing (ICS)."},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2906199"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942068"},{"key":"e_1_3_2_22_2","volume-title":"ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)","author":"Langhammer M.","year":"2020","unstructured":"M. Langhammer, S. Gribok, and G. Baeckler. 2020. High density pipelined 8bit multiplier systolic arrays for FPGA. In ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)."},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00027"},{"key":"e_1_3_2_24_2","article-title":"Deep learning with INT8 optimization on Xilinx devices","author":"Fu Y.","year":"2017","unstructured":"Y. Fu, E. Wu, A. Sirasao, S. Attia, K. Khan, and R. Wittig. 2017. Deep learning with INT8 optimization on Xilinx devices. White Paper (2017). https:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp486-deep-learning-int8.pdf.","journal-title":"White Paper"},{"key":"e_1_3_2_25_2","volume-title":"Asia & South Pacific Design Automation Conference (ASP-DAC)","author":"Zervakis G.","year":"2021","unstructured":"G. Zervakis, H. Saadat, H. Amrouch, A. Gerstlauer, S. Parameswaran, and J. Henkel. 2021. Approximate computing for ML: State-of-the-art, challenges and visions. In Asia & South Pacific Design Automation Conference (ASP-DAC)."},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1962.5219391"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3028350"},{"key":"e_1_3_2_28_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Saadat H.","year":"2020","unstructured":"H. Saadat, H. Javaid, A. Ignjatovic, and S. Parameswaran. 2020. REALM: Reduced-error approximate log-based integer multiplier. In Design, Automation & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2940943"},{"issue":"12","key":"e_1_3_2_30_2","article-title":"Weight-oriented approximation for energy-efficient neural network inference accelerators","volume":"67","author":"Tasoulas Z. G.","year":"2020","unstructured":"Z. G. Tasoulas, G. Zervakis, I. Anagnostopoulos, H. Amrouch, and J. Henkel. 2020. Weight-oriented approximation for energy-efficient neural network inference accelerators. IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers 67, 12 (2020).","journal-title":"IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TBME.1985.325532"},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3006451"},{"key":"e_1_3_2_33_2","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967005"},{"issue":"9","key":"e_1_3_2_34_2","article-title":"Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers","volume":"67","author":"Strollo A. G. M.","year":"2020","unstructured":"A. G. M. Strollo, E. Napoli, D. De Caro, N. Petra, and G. D. Meo. 2020. Comparison and extension of approximate 4-2 compressors for low-power approximate multipliers. IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers 67, 9 (2020).","journal-title":"IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers"},{"key":"e_1_3_2_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2643003"},{"key":"e_1_3_2_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2643639"},{"issue":"12","key":"e_1_3_2_37_2","article-title":"Approximate multipliers based on new approximate compressors","volume":"65","author":"Esposito D.","year":"2018","unstructured":"D. Esposito, A. G. M. Strollo, E. Napoli, D. De Caro, and N. Petra. 2018. Approximate multipliers based on new approximate compressors. IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers 65, 12 (2018).","journal-title":"IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers"},{"key":"e_1_3_2_38_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9181066"},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2978773"},{"key":"e_1_3_2_40_2","volume-title":"Asia & South Pacific Design Automation Conference (ASP-DAC)","author":"Guo Y.","year":"2020","unstructured":"Y. Guo, H. Sun, and S. Kimura. 2020. Small-area and low-power FPGA-based multipliers using approximate elementary modules. In Asia & South Pacific Design Automation Conference (ASP-DAC)."},{"key":"e_1_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2953751"},{"key":"e_1_3_2_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702363"},{"issue":"3","key":"e_1_3_2_43_2","article-title":"Design, evaluation and application of approximate high-radix dividers","volume":"4","author":"Chen L.","year":"2018","unstructured":"L. Chen, J. Han, W. Liu, P. Montuschi, and F. Lombardi. 2018. Design, evaluation and application of approximate high-radix dividers. IEEE Trans. Multi-scale Comput. Syst. 4, 3 (2018).","journal-title":"IEEE Trans. Multi-scale Comput. Syst."},{"key":"e_1_3_2_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2494005"},{"key":"e_1_3_2_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2916817"},{"key":"e_1_3_2_46_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Jiang H.","year":"2018","unstructured":"H. Jiang, L. Liu, F. Lombardi, and J. Han. 2018. Adaptive approximation in arithmetic circuits: A low-power unsigned divider design. In Design, Automation & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_47_2","volume-title":"International Symposium on Low Power Electronics and Design (ISLPED)","author":"Vaeztourshizi M.","year":"2018","unstructured":"M. Vaeztourshizi, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. 2018. An energy-efficient, yet highly-accurate, approximate non-iterative divider. In International Symposium on Low Power Electronics and Design (ISLPED)."},{"key":"e_1_3_2_48_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Vahdat S.","year":"2017","unstructured":"S. Vahdat, M. Kamal, A. Afzali-Kusha, M. Pedram, and Z. Navabi. 2017. TruncApp: A truncation-based approximate divider for energy efficient DSP applications. In Design, Automation & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2890712"},{"issue":"12","key":"e_1_3_2_50_2","article-title":"Approximate multipliers with dynamic truncation for energy reduction via graceful quality degradation","volume":"67","author":"Frustaci F.","year":"2020","unstructured":"F. Frustaci, S. Perri, P. Corsonello, and M. Alioto. 2020. Approximate multipliers with dynamic truncation for energy reduction via graceful quality degradation. IEEE Trans. Circ. Syst. II (TCAS-II): Expr. Briefs 67, 12 (2020).","journal-title":"IEEE Trans. Circ. Syst. II (TCAS-II): Expr. Briefs"},{"key":"e_1_3_2_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372600"},{"key":"e_1_3_2_52_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2587696"},{"key":"e_1_3_2_53_2","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2897965"},{"key":"e_1_3_2_54_2","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196115"},{"key":"e_1_3_2_55_2","volume-title":"Asia & South Pacific Design Automation Conference (ASP-DAC)","author":"Ebrahimi Z.","year":"2020","unstructured":"Z. Ebrahimi, S. Ullah, and A. Kumar. 2020. LeAp: Leading-one detection-based softcore approximate multipliers with tunable accuracy. In Asia & South Pacific Design Automation Conference (ASP-DAC)."},{"key":"e_1_3_2_56_2","volume-title":"Design, Automation, & Test in Europe Conference (DATE)","author":"Imani M.","year":"2019","unstructured":"M. Imani, R. Garcia, A. Huang, and T. Rosing. 2019. CADE: Configurable approximate divider for energy efficiency. In Design, Automation, & Test in Europe Conference (DATE)."},{"issue":"3","key":"e_1_3_2_57_2","article-title":"Low-power approximate multipliers using encoded partial products and approximate compressors","volume":"8","author":"Ansari M. S.","year":"2018","unstructured":"M. S. Ansari, H. Jiang, B. F. Cockburn, and J. Han. 2018. Low-power approximate multipliers using encoded partial products and approximate compressors. IEEE J. Emerg. Select. Topics Circ. Syst. 8, 3 (2018).","journal-title":"IEEE J. Emerg. Select. Topics Circ. Syst."},{"key":"e_1_3_2_58_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Mrazek V.","year":"2017","unstructured":"V. Mrazek, R. Hrbacek, Z. Vasicek, and L. Sekanina. 2017. EvoApprox8b: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. In Design, Automation & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_59_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Zendegani R.","year":"2016","unstructured":"R. Zendegani, M. Kamal, A. Fayyazi, A. Afzali-Kusha, S. Safari, and M. Pedram. 2016. SEERAD: A high speed yet energy-efficient rounding-based approximate divider. In Design, Automation & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_60_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926083"},{"key":"e_1_3_2_61_2","volume-title":"Asia & South Pacific Design Automation Conference (ASP-DAC)","author":"Behroozi S.","year":"2019","unstructured":"S. Behroozi, J. Li, J. Melchert, and Y. Kim. 2019. SAADI: A scalable accuracy approximate divider for dynamic energy-quality scaling. In Asia & South Pacific Design Automation Conference (ASP-DAC)."},{"key":"e_1_3_2_62_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Ansari M. S.","year":"2019","unstructured":"M. S. Ansari, B. F. Cockburn, and J. Han. 2019. A hardware-efficient logarithmic multiplier with improved accuracy. In Design, Automation & Test in Europe Conference (DATE)."},{"issue":"9","key":"e_1_3_2_63_2","article-title":"Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications","volume":"65","author":"Liu W.","year":"2018","unstructured":"W. Liu, J. Xu, D. Wang, C. Wang, P. Montuschi, and F. Lombardi. 2018. Design and evaluation of approximate logarithmic multipliers for low power error-tolerant applications. IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers 65, 9 (2018).","journal-title":"IEEE Trans. Circ. Syst. I (TCAS-I): Reg. Papers"},{"key":"e_1_3_2_64_2","article-title":"Reduced-precision strategies for bounded memory in deep neural nets","author":"Judd P.","year":"2015","unstructured":"P. Judd, J. Albericio, T. Hetherington, T. Aamodt, N. E. Jerger, R. Urtasun, and A. Moshovos. 2015. Reduced-precision strategies for bounded memory in deep neural nets. arXiv preprint (2015).","journal-title":"arXiv preprint"},{"issue":"4","key":"e_1_3_2_65_2","article-title":"Energy efficient neural computing: A study of cross-layer approximations","volume":"8","author":"Sarwar S.","year":"2018","unstructured":"S. Sarwar, G. Srinivasan, B. Han, P. Wijesinghe, A. Jaiswal, P. Panda, A. Raghunathan, and K. Roy. 2018. Energy efficient neural computing: A study of cross-layer approximations. IEEE J. Emerg. Select. Topics Circ. Syst 8, 4 (Dec. 2018).","journal-title":"IEEE J. Emerg. Select. Topics Circ. Syst"},{"key":"e_1_3_2_66_2","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2018.1575"},{"key":"e_1_3_2_67_2","volume-title":"Design, Automation, & Test in Europe Conference (DATE)","author":"Lee S.","year":"2017","unstructured":"S. Lee, L. K. John, and A. Gerstlauer. 2017. High-level synthesis of approximate hardware under joint precision and voltage scaling. In Design, Automation, & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_68_2","volume-title":"ACM\/IEEE Design Automation Conference (DAC)","author":"Chippa V. K.","year":"2013","unstructured":"V. K. Chippa, S. T. Chakradhar, K. Roy, and A. Raghunathan. 2013. Analysis and characterization of inherent application resilience for approximate computing. In ACM\/IEEE Design Automation Conference (DAC)."},{"key":"e_1_3_2_69_2","volume-title":"ACM Computing Frontiers Conference (CF)","author":"Gillani G. A.","year":"2017","unstructured":"G. A. Gillani and A. B. J. Kokkeler. 2017. Improving error resilience analysis methodology of iterative workloads for approximate computing. In ACM Computing Frontiers Conference (CF)."},{"issue":"5","key":"e_1_3_2_70_2","article-title":"ASAC: Automatic sensitivity analysis for approximate computing","volume":"49","author":"Roy P.","year":"2014","unstructured":"P. Roy, R. Ray, C. Wang, and W. F. Wong. 2014. ASAC: Automatic sensitivity analysis for approximate computing. ACM Conference on Languages, Compilers and Tools for Embedded Systems (LCTEC) 49, 5 (2014).","journal-title":"ACM Conference on Languages, Compilers and Tools for Embedded Systems (LCTEC)"},{"key":"e_1_3_2_71_2","volume-title":"International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","author":"Roy P.","year":"2015","unstructured":"P. Roy, J. Wang, and W. F. Wong. 2015. PAC: Program analysis for approximation-aware compilation. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)."},{"key":"e_1_3_2_72_2","volume-title":"Design, Automation, & Test in Europe Conference (DATE)","author":"Hanif M. A.","year":"2018","unstructured":"M. A. Hanif, R. Hafiz, and M. Shafique. 2018. Error resilience analysis for systematically employing approximate computing in convolutional neural networks. In Design, Automation, & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_73_2","volume-title":"Design, Automation, & Test in Europe Conference (DATE)","author":"Schorn C.","year":"2018","unstructured":"C. Schorn, A. Guntoro, and G. Ascheid. 2018. Accurate neuron resilience prediction for a flexible reliability management in neural network accelerators. In Design, Automation, & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_74_2","article-title":"Methods for interpreting and understanding deep neural networks","volume":"73","author":"Montavon G.","year":"2018","unstructured":"G. Montavon, W. Samek, and K. M\u00fcller. 2018. Methods for interpreting and understanding deep neural networks. Dig. Sig. Process. 73 (2018).","journal-title":"Dig. Sig. Process."},{"key":"e_1_3_2_75_2","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH47378.2019.181283"},{"key":"e_1_3_2_76_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.patcog.2016.11.008"},{"issue":"4","key":"e_1_3_2_77_2","article-title":"Libraries of approximate circuits: Automated design and application in CNN Accelerators","volume":"10","author":"Mrazek V.","year":"2020","unstructured":"V. Mrazek, L. Sekanina, and Z. Vasicek. 2020. Libraries of approximate circuits: Automated design and application in CNN Accelerators. IEEE J. Emerg. Select. Topics Circ. Syst 10, 4 (2020).","journal-title":"IEEE J. Emerg. Select. Topics Circ. Syst"},{"key":"e_1_3_2_78_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-99322-5_9"},{"key":"e_1_3_2_79_2","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2016.2598283"},{"key":"e_1_3_2_80_2","volume-title":"IEEE\/ACM Design Automation Conference (DAC)","author":"Huang J.","year":"2012","unstructured":"J. Huang, J. Lach, and G. Robins. 2012. A methodology for energy-quality trade-off using imprecise hardware. In IEEE\/ACM Design Automation Conference (DAC)."},{"key":"e_1_3_2_81_2","volume-title":"International Symposium on Quality Electronic Design (ISQED)","author":"Lee S.","year":"2016","unstructured":"S. Lee, D. Lee, K. Han, E. Shriver, L. K. John, and A. Gerstlauer. 2016. Statistical quality modeling of approximate hardware. In International Symposium on Quality Electronic Design (ISQED)."},{"key":"e_1_3_2_82_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2019.04.003"},{"key":"e_1_3_2_83_2","volume-title":"Design, Automation, & Test in Europe Conference (DATE)","author":"Moussawi A. H. El","year":"2017","unstructured":"A. H. El Moussawi and S. Derrien. 2017. Superword level parallelism aware word length optimization. In Design, Automation, & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_84_2","volume-title":"Design, Automation, & Test in Europe Conference (DATE)","author":"Ha V. P.","year":"2020","unstructured":"V. P. Ha, T. Yuki, and O. Sentieys. 2020. Towards generic and scalable word-length optimization. In Design, Automation, & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_85_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2975695"},{"key":"e_1_3_2_86_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Parra C. De la","year":"2020","unstructured":"C. De la Parra, A. Guntoro, and A. Kumar. 2020. ProxSim: GPU-based simulation framework for cross-layer approximate DNN optimization. In Design, Automation & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_87_2","article-title":"Improving approximate neural networks for perception tasks through specialized optimization","volume":"113","author":"Parra C. De la","year":"2020","unstructured":"C. De la Parra, A. Guntoro, and A. Kumar. 2020. Improving approximate neural networks for perception tasks through specialized optimization. Fut. Gen. Comput. Syst. 113 (2020).","journal-title":"Fut. Gen. Comput. Syst."},{"key":"e_1_3_2_88_2","volume-title":"Design, Automation & Test in Europe Conference (DATE)","author":"Bosio A.","year":"2019","unstructured":"A. Bosio, D. Menard, and O. Sentieys. 2019. A comprehensive analysis of approximate computing techniques: From component-to application-level. In Design, Automation & Test in Europe Conference (DATE)."},{"key":"e_1_3_2_89_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.3029453"},{"key":"e_1_3_2_90_2","volume-title":"IEEE International Symposium on Circuits and Systems (ISCAS)","author":"Venkataramani S.","year":"2021","unstructured":"S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, Hoang Tran et\u00a0al. 2021. RaPiD: AI accelerator for ultra-low precision training and inference. IEEE International Symposium on Circuits and Systems (ISCAS)."},{"key":"e_1_3_2_91_2","volume-title":"ACM Great Lakes Symposium on VLSI (GLSVLSI)","author":"Yin P.","year":"2018","unstructured":"P. Yin, C. Wang, W. Liu, and F. Lombardi. 2018. Design of dynamic range approximate logarithmic multipliers. In ACM Great Lakes Symposium on VLSI (GLSVLSI)."},{"key":"e_1_3_2_92_2","volume-title":"Asia & South Pacific Design Automation Conference (ASP-DAC)","author":"Fan Y.","year":"2019","unstructured":"Y. Fan, Xiaoxi Wu, Jiying Dong, and Zhi Qi. 2019. AxDNN: Towards cross-layer design of approximate DNNs. In Asia & South Pacific Design Automation Conference (ASP-DAC)."},{"key":"e_1_3_2_93_2","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317933"},{"key":"e_1_3_2_94_2","doi-asserted-by":"publisher","DOI":"10.1145\/3126565"},{"key":"e_1_3_2_95_2","doi-asserted-by":"publisher","DOI":"10.1109\/AIPR47015.2019.9174580"},{"key":"e_1_3_2_96_2","volume-title":"Alvey Vision Conference (AVC)","author":"Harris C.","year":"1988","unstructured":"C. Harris and M. Stephens. 1988. A combined corner and edge detector. In Alvey Vision Conference (AVC), Vol. 15."},{"key":"e_1_3_2_97_2","doi-asserted-by":"publisher","DOI":"10.5201\/ipol.2018.229"},{"key":"e_1_3_2_98_2","volume-title":"The Designer\u2019s Guide to VHDL","author":"Ashenden P.","year":"2010","unstructured":"P. Ashenden. 2010. The Designer\u2019s Guide to VHDL. Morgan Kaufmann."},{"key":"e_1_3_2_99_2","volume-title":"Computer Arithmetic: Algorithms and Hardware Designs","author":"Parhami B.","year":"2010","unstructured":"B. Parhami. 2010. Computer Arithmetic: Algorithms and Hardware Designs. Vol. 20. Oxford University Press."},{"key":"e_1_3_2_100_2","article-title":"Xilinx 7 Series FPGA Programmable Guide for HDL Designs","year":"2013","unstructured":"Xilinx. 2013. Xilinx 7 Series FPGA Programmable Guide for HDL Designs. Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx14_7\/7series_hdl.pdf.","journal-title":"Retrieved from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx14_7\/7series_hdl.pdf"},{"key":"e_1_3_2_101_2","doi-asserted-by":"publisher","DOI":"10.1161\/01.CIR.101.23.e215"},{"key":"e_1_3_2_102_2","volume-title":"European Conference on Computer Vision (ECCV)","author":"Mueller M.","year":"2016","unstructured":"M. Mueller, N. Smith, and B. Ghanem. 2016. A benchmark and simulator for UAV tracking. In European Conference on Computer Vision (ECCV)."},{"key":"e_1_3_2_103_2","volume-title":"Workshops in European Conference on Computer Vision (ECCV)","author":"Fan H.","year":"2020","unstructured":"H. Fan, Longyin Wen, Dawei Du, Pengfei Zhu, Qinghua Hu, Haibin Ling, Mubarak Shah, Biao Wang, Bin Dong, Di Yuan, Dong Wang, Dongjie Zhou, Haoyang Sun, Hossein Ghanei-Yakhdan, Huchuan Lu, Javad Khaghani, Jinghao Zhou, Keyang Wang, Lei Pang, Lei Zhang, Li Cheng, Liting Lin, Lu Ding, Nana Fan, Peng Wang, Penghao Zhang, Ruiyan Ma, Seyed Mojtaba Marvasti-Zadeh, Shohreh Kasaei, Shuhao Chen, Simiao Lai, Tianyang Xu, Wentao He, Xiaojun Wu, Xin Hou, Xuefeng Zhu, Yanjie Gao, Yanyun Zhao, Yong Wang, Yong Xu, Yubo Sun, Yuting Yang, Yuxuan Li, Zezhou Wang, Zhenwei He, Zhenyu He, Zhipeng Luo, Zhongjian Huang, Zhongzhou Zhang, Zikai Zhang, and Zitong Yi. 2020. VisDrone-SOT2020: The vision meets drone single object tracking challenge results. In Workshops in European Conference on Computer Vision (ECCV)."},{"key":"e_1_3_2_104_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.isprsjprs.2020.05.009"},{"key":"e_1_3_2_105_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2630270"},{"key":"e_1_3_2_106_2","volume-title":"Real-time Image and Video Processing (RTIVP)","author":"Jridi M.","year":"2013","unstructured":"M. Jridi, Y. Ouerhani, and A. Alfalou. 2013. Low complexity DCT engine for image and video compression. In Real-time Image and Video Processing (RTIVP), Vol. 8656."},{"key":"e_1_3_2_107_2","volume-title":"IEEE Access","volume":"8","author":"Nomani T.","year":"2020","unstructured":"T. Nomani, M. Mohsin, Z. Pervaiz, and M. Shafique. 2020. xUAVs: Towards efficient approximate computing for UAVs\u2014Low power approximate adders with single LUT Delay for FPGA-based aerial imaging optimization. IEEE Access 8 (2020)."},{"key":"e_1_3_2_108_2","unstructured":"SmartCardia. 2018. 32-bit ARM Cortex-M3 inside SmartCardia-INYU. https:\/\/smartcardia.com\/."},{"key":"e_1_3_2_109_2","article-title":"7 Series FPGAs Configuration User Guide (UG470)","year":"2018","unstructured":"Xilinx. 2018. 7 Series FPGAs Configuration User Guide (UG470). https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug470_7Series_Config.pdf.","journal-title":"https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug470_7Series_Config.pdf"},{"key":"e_1_3_2_110_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2812118"},{"key":"e_1_3_2_111_2","doi-asserted-by":"crossref","unstructured":"Z. Ebrahimi and A. Kumar. 2021. BioCare: An energy-efficient CGRA for bio-signal processing at the edge. In International Symposium on Circuits and Systems (ISCAS) .","DOI":"10.1109\/ISCAS51556.2021.9401461"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3486616","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3486616","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:12:06Z","timestamp":1750191126000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3486616"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11,2]]},"references-count":110,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2022,3,31]]}},"alternative-id":["10.1145\/3486616"],"URL":"https:\/\/doi.org\/10.1145\/3486616","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2021,11,2]]},"assertion":[{"value":"2021-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-08-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2021-11-02","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}