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IEEE Computer Society, Amsterdam, The Netherlands, 401--407."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-06859-7_145"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1980.1653418"},{"volume-title":"International Symposium on Computer Architecture (ISCA), W.K. King and O. Garcia (Eds.). ACM","author":"Dennis J.B.","key":"e_1_3_2_1_40_1","unstructured":"J.B. Dennis and D.P. Misunas . 1975. A Preliminary Architecture for a Basic Dataflow Processor . In International Symposium on Computer Architecture (ISCA), W.K. King and O. Garcia (Eds.). ACM , Houston, TX, USA, 126--132. J.B. Dennis and D.P. Misunas. 1975. A Preliminary Architecture for a Basic Dataflow Processor. In International Symposium on Computer Architecture (ISCA), W.K. King and O. Garcia (Eds.). ACM, Houston, TX, USA, 126--132."},{"key":"e_1_3_2_1_41_1","unstructured":"J. Eker and J.W. Janneck. 2002. CAL Actor Language - Language report. EECS Department University of California at Berkeley. J. Eker and J.W. Janneck. 2002. CAL Actor Language - Language report. EECS Department University of California at Berkeley."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653942"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-005-0290-3"},{"volume-title":"International Symposium on Parallel Algorithms Architecture Synthesis. IEEE Computer Society, Aizu-Wakamatsu, Japan.","author":"Gaudiot J.-L.","key":"e_1_3_2_1_44_1","unstructured":"J.-L. Gaudiot , T. DeBoni , J. Feo , W. B\u00f6hm , W. Najjar , and P. Miller . 1997. The SISAL model of functional programming and its implementation . In International Symposium on Parallel Algorithms Architecture Synthesis. IEEE Computer Society, Aizu-Wakamatsu, Japan. J.-L. Gaudiot, T. DeBoni, J. Feo, W. B\u00f6hm, W. Najjar, and P. Miller. 1997. The SISAL model of functional programming and its implementation. In International Symposium on Parallel Algorithms Architecture Synthesis. IEEE Computer Society, Aizu-Wakamatsu, Japan."},{"key":"e_1_3_2_1_45_1","volume-title":"Requirements on the Execution of Kahn Process Networks. In European Symposium on Programming (ESOP) (LNCS","volume":"334","author":"Geilen M.","unstructured":"M. Geilen and T. Basten . 2003 . Requirements on the Execution of Kahn Process Networks. In European Symposium on Programming (ESOP) (LNCS , Vol. 2618), P. Degano (Ed.). Springer, Warsaw, Poland, 319-- 334 . M. Geilen and T. Basten. 2003. Requirements on the Execution of Kahn Process Networks. In European Symposium on Programming (ESOP) (LNCS, Vol. 2618), P. Degano (Ed.). Springer, Warsaw, Poland, 319--334."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"crossref","unstructured":"V. Govindaraju C.-H. Ho T. Nowatzki J. Chhugani N. Satish K. Sankaralingam and C. Kim. 2012. DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing. IEEE Micro 33 5 (2012). V. Govindaraju C.-H. Ho T. Nowatzki J. Chhugani N. Satish K. Sankaralingam and C. Kim. 2012. DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing. IEEE Micro 33 5 (2012).","DOI":"10.1109\/MM.2012.51"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/74926.74930"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2465.2468"},{"volume-title":"Formal Methods and Models for Codesign (MEMOCODE)","author":"Halbwachs N.","key":"e_1_3_2_1_49_1","unstructured":"N. Halbwachs . 2005. A synchronous language at work: the story of Lustre . In Formal Methods and Models for Codesign (MEMOCODE) . IEEE Computer Society , Verona, Italy , 3--11. N. Halbwachs. 2005. A synchronous language at work: the story of Lustre. In Formal Methods and Models for Codesign (MEMOCODE). IEEE Computer Society, Verona, Italy, 3--11."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.97300"},{"key":"e_1_3_2_1_51_1","doi-asserted-by":"publisher","DOI":"10.1109\/CMPASS.1996.507878"},{"key":"e_1_3_2_1_52_1","volume-title":"Recognizing Leveled-Planar DAGs in Linear Time. In Graph Drawing (GD) (LNCS","volume":"311","author":"Heath L.S.","unstructured":"L.S. Heath and S.V. Pemmaraju . 1996 . Recognizing Leveled-Planar DAGs in Linear Time. In Graph Drawing (GD) (LNCS , Vol. 1027), F.J. Brandenburg (Ed.). Springer, Passau, Germany, 300-- 311 . L.S. Heath and S.V. Pemmaraju. 1996. Recognizing Leveled-Planar DAGs in Linear Time. In Graph Drawing (GD) (LNCS, Vol. 1027), F.J. Brandenburg (Ed.). Springer, Passau, Germany, 300--311."},{"key":"e_1_3_2_1_53_1","doi-asserted-by":"publisher","DOI":"10.1137\/S0097539795291550"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/32.9065"},{"key":"e_1_3_2_1_55_1","volume-title":"Operation-Triggering. In Compiler Construction (CC) (LNCS","volume":"449","author":"J. Hoogerbrugge and H. Corp","unstructured":"J. Hoogerbrugge and H. Corp oraal . 1994. Transport-Triggering vs . Operation-Triggering. In Compiler Construction (CC) (LNCS , Vol. 786), P. Fritzson (Ed.). Springer, Edinburgh, UK, 435-- 449 . J. Hoogerbrugge and H. Corporaal. 1994. Transport-Triggering vs. Operation-Triggering. In Compiler Construction (CC) (LNCS, Vol. 786), P. Fritzson (Ed.). Springer, Edinburgh, UK, 435--449."},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1006\/inco.2000.2917"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1988.5222"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1145\/1013208.1013209"},{"volume-title":"Transport-Triggered Soft Cores. In Intern. Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE Comp. Soc.","author":"J\u00e4\u00e4skel\u00e4inen P.","key":"e_1_3_2_1_59_1","unstructured":"P. J\u00e4\u00e4skel\u00e4inen , A. Tervo , G.P. Vay\u00e1 , T. Viitanen , N. Behmann , and H. Blume . 2018 . Transport-Triggered Soft Cores. In Intern. Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE Comp. Soc. , Vancouver, BC, Canada. P. J\u00e4\u00e4skel\u00e4inen, A. Tervo, G.P. Vay\u00e1, T. Viitanen, N. Behmann, and H. Blume. 2018. Transport-Triggered Soft Cores. In Intern. Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE Comp. Soc., Vancouver, BC, Canada."},{"volume-title":"The Semantics of a Simple Language for Parallel Programming","author":"Kahn G.","key":"e_1_3_2_1_60_1","unstructured":"G. Kahn . 1974. The Semantics of a Simple Language for Parallel Programming . In Information Processing, J.L. Rosenfeld (Ed.). North-Holland, Stockholm , Sweden , 471--475. G. Kahn. 1974. The Semantics of a Simple Language for Parallel Programming. In Information Processing, J.L. Rosenfeld (Ed.). North-Holland, Stockholm, Sweden, 471--475."},{"volume-title":"Coroutines and networks of parallel processes","author":"Kahn G.","key":"e_1_3_2_1_61_1","unstructured":"G. Kahn and D.B. MacQueen . 1977. Coroutines and networks of parallel processes . In Information Processing, B. Gilchrist (Ed.). North-Holland , 993--998. G. Kahn and D.B. MacQueen. 1977. Coroutines and networks of parallel processes. In Information Processing, B. Gilchrist (Ed.). North-Holland, 993--998."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1137\/0114108"},{"volume-title":"Formal Description of Programming Concepts","author":"Keller R.M.","key":"e_1_3_2_1_63_1","unstructured":"R.M. Keller . 1978. Denotational Models for Parallel Programs with Indeterminate Operators . In Formal Description of Programming Concepts , E.J. Neuhold (Ed.). North-Holland , 337--366. R.M. Keller. 1978. Denotational Models for Parallel Programs with Indeterminate Operators. In Formal Description of Programming Concepts, E.J. Neuhold (Ed.). North-Holland, 337--366."},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-16442-1_18"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.97301"},{"key":"e_1_3_2_1_66_1","first-page":"330","article-title":"Recurrences, iteration, and conditionals in statically scheduled block diagrams languages. In VLSI Signal Processing III. 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In International Symposium on Computer Architecture (ISCA). IEEE Computer Society, Jerusalem, Israel, 262--272."},{"key":"e_1_3_2_1_74_1","first-page":"284","article-title":"Id (Version 90.1) Reference Manual","author":"Nikhil R.S.","year":"1991","unstructured":"R.S. Nikhil . 1991 . Id (Version 90.1) Reference Manual . Technical Report CSG Memo 284 - 282 . MIT Lab for Computer Science, Cambridge, MA, USA. R.S. Nikhil. 1991. Id (Version 90.1) Reference Manual. Technical Report CSG Memo 284-2. MIT Lab for Computer Science, Cambridge, MA, USA.","journal-title":"Technical Report CSG Memo"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"crossref","unstructured":"T. Nipkow and G. Klein. 2015. Concrete Semantics with Isabelle\/HOL. Springer. T. Nipkow and G. Klein. 2015. Concrete Semantics with Isabelle\/HOL. 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In International Symposium on Computer Architecture (ISCA), J.-L. Baer and L. Snyder (Eds.). IEEE Computer Society , Seattle, Washington, USA, 82--91. G. Papadopoulos and D. Culler. 1990. Monsoon: An Explicit Token-Store Architecture. In International Symposium on Computer Architecture (ISCA), J.-L. Baer and L. Snyder (Eds.). IEEE Computer Society, Seattle, Washington, USA, 82--91."},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1016\/0304-3975(77)90044-5"},{"key":"e_1_3_2_1_81_1","first-page":"2","article-title":"A Data Flow Multiprocessor","volume":"26","author":"Rumbaugh J.","year":"1977","unstructured":"J. Rumbaugh . 1977 . A Data Flow Multiprocessor . IEEE Transactions on Computers (T-C) 26 , 2 (February 1977), 138--146. J. Rumbaugh. 1977. A Data Flow Multiprocessor. IEEE Transactions on Computers (T-C) 26, 2 (February 1977), 138--146.","journal-title":"IEEE Transactions on Computers (T-C)"},{"key":"e_1_3_2_1_82_1","article-title":"TRIPS: A Polymorphous Architecture for Exploiting ILP, TLP, and DLP","volume":"1","author":"Sankaralingam K.","year":"2004","unstructured":"K. Sankaralingam , R. Nagarajan , H. Liu , C. Kim , J. Huh , N. Ranganathan , D. Burger , S.W. Keckler , R.G. Mcdonald , and C.R. Moore . 2004 . TRIPS: A Polymorphous Architecture for Exploiting ILP, TLP, and DLP . ACM Transactions on Architecture and Code Optimization (TACO) 1 , 1 (2004). K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, N. Ranganathan, D. Burger, S.W. Keckler, R.G. Mcdonald, and C.R. Moore. 2004. TRIPS: A Polymorphous Architecture for Exploiting ILP, TLP, and DLP. ACM Transactions on Architecture and Code Optimization (TACO) 1, 1 (2004).","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"e_1_3_2_1_83_1","unstructured":"J.A. Sharp (Ed.). 1992. Data Flow Computing - Theory and Practice. Ablex Publishing. J.A. Sharp (Ed.). 1992. Data Flow Computing - Theory and Practice. Ablex Publishing."},{"key":"e_1_3_2_1_84_1","unstructured":"J. Singer. 2002. Efficiently Computing the Static Single Information Form. J. Singer. 2002. Efficiently Computing the Static Single Information Form."},{"volume-title":"Microarchitecture (MICRO)","author":"Stoutchinin A.","key":"e_1_3_2_1_85_1","unstructured":"A. Stoutchinin and F. de Ferri\u00e8re . 2001. Efficient static single assignment form for predication . In Microarchitecture (MICRO) . IEEE Computer Society, Austin , Texas, USA , 172--181. A. Stoutchinin and F. de Ferri\u00e8re. 2001. Efficient static single assignment form for predication. In Microarchitecture (MICRO). IEEE Computer Society, Austin, Texas, USA, 172--181."},{"key":"e_1_3_2_1_87_1","unstructured":"S. Swanson K. Michelson A. Schwerin and M. Oskin. 2003. WaveScalar. In Microarchitecture (MICRO). IEEE Computer Society San Diego CA USA 291--302. S. Swanson K. Michelson A. Schwerin and M. Oskin. 2003. WaveScalar. In Microarchitecture (MICRO). IEEE Computer Society San Diego CA USA 291--302."},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1145\/1233307.1233308"},{"key":"e_1_3_2_1_89_1","unstructured":"A. Tavares M. Bigonha R.S. Bigonha B. Boissinot F.M.Q. Pereira and F. Rastello. 2012. SSI revisited: A Program Representation for Sparse Data-flow Analyses. Preprint submitted to Science of Computer Programming. A. Tavares M. Bigonha R.S. Bigonha B. Boissinot F.M.Q. Pereira and F. Rastello. 2012. SSI revisited: A Program Representation for Sparse Data-flow Analyses. Preprint submitted to Science of Computer Programming."},{"volume-title":"Efficient SSI Conversion. Brazilian Symposium on Programming Languages (SBLP).","author":"Tavares A.L.C.","key":"e_1_3_2_1_90_1","unstructured":"A.L.C. Tavares , F.M.Q. Pereira , M.A.S. Bigonha , and R.S. Bigonha . 2010 . Efficient SSI Conversion. Brazilian Symposium on Programming Languages (SBLP). A.L.C. Tavares, F.M.Q. Pereira, M.A.S. Bigonha, and R.S. Bigonha. 2010. Efficient SSI Conversion. Brazilian Symposium on Programming Languages (SBLP)."},{"volume-title":"Design Decisions in the Implementation of a RAW Architecture Workstation. Master's thesis. Department of Electrical Engineering and Computer Science","author":"Taylor M.B.","key":"e_1_3_2_1_91_1","unstructured":"M.B. Taylor . 1999. Design Decisions in the Implementation of a RAW Architecture Workstation. Master's thesis. Department of Electrical Engineering and Computer Science , MIT , Cambridge, MA, USA . M.B. Taylor. 1999. Design Decisions in the Implementation of a RAW Architecture Workstation. Master's thesis. Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA, USA."},{"key":"e_1_3_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"volume-title":"Overview of the Monsoon Project. In International Conference on Computer Design (ICCD). IEEE Computer Society","author":"Traub K.R.","key":"e_1_3_2_1_94_1","unstructured":"K.R. Traub , G.M. Papadopoulos , M.J. Beckerle , J.E. Hicks , and J. Young . 1991 . Overview of the Monsoon Project. In International Conference on Computer Design (ICCD). IEEE Computer Society , Cambridge, MA, USA, 150--155. K.R. Traub, G.M. Papadopoulos, M.J. Beckerle, J.E. Hicks, and J. Young. 1991. Overview of the Monsoon Project. In International Conference on Computer Design (ICCD). IEEE Computer Society, Cambridge, MA, USA, 150--155."},{"key":"e_1_3_2_1_95_1","doi-asserted-by":"crossref","unstructured":"T. Ungerer. 1993. Datenflu\u00dfrechner. Teubner. T. Ungerer. 1993. Datenflu\u00dfrechner. Teubner.","DOI":"10.1007\/978-3-322-94688-1"},{"key":"e_1_3_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1145\/27633.28055"},{"key":"e_1_3_2_1_97_1","unstructured":"A.H. Veen. 1986. The misconstrued semicolon: reconciling imperative languages and dataflow machines. Centrum voor Wiskunde en Informatica Amsterdam The Netherlands. A.H. Veen. 1986. The misconstrued semicolon: reconciling imperative languages and dataflow machines. Centrum voor Wiskunde en Informatica Amsterdam The Netherlands."},{"key":"e_1_3_2_1_99_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.612254"},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653941"},{"key":"e_1_3_2_1_101_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2013.125"},{"volume-title":"Fall Joint Computer Conf. on Exploring Technology: today and tomorrow (FJCC), S.A. Szygenda (Ed.). ACM","author":"Yuba T.","key":"e_1_3_2_1_102_1","unstructured":"T. Yuba , K. Hiraki , T. Shimada , S. Sekiguchi , and K. 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