{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,23]],"date-time":"2026-02-23T23:10:11Z","timestamp":1771888211845,"version":"3.50.1"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2023,1,18]],"date-time":"2023-01-18T00:00:00Z","timestamp":1674000000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NSF","award":["CNS-1749845 and CNS-1902532"],"award-info":[{"award-number":["CNS-1749845 and CNS-1902532"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2023,3,31]]},"abstract":"<jats:p>In this article, we present and evaluate a true random number generator (TRNG) design that is compatible with the restrictions imposed by cloud-based Field Programmable Gate Array (FPGA) providers such as Amazon Web Services (AWS) EC2 F1. Because cloud FPGA providers disallow the ring oscillator circuits that conventionally generate TRNG entropy, our design is oscillator-free and uses clock jitter as its entropy source. The clock jitter is harvested with a time-to-digital converter (TDC) and a controllable delay line that is continuously tuned to compensate for process, voltage, and temperature variations. After describing the design, we present and validate a stochastic model that conservatively quantifies its worst-case entropy. We deploy and model the design in the cloud on 60 EC2 F1 FPGA instances to ensure sufficient randomness is captured. TRNG entropy is further validated using NIST test suites, and experiments are performed to understand how the TRNG responds to on-die power attacks that disturb the FPGA supply voltage in the vicinity of the TRNG. After introducing and validating our basic TRNG design, we introduce and validate a new variant that uses four instances of a linkable sampling module to increase the entropy per sample and improve throughput. The new variant improves throughput by 250% at a modest 17% increase in CLB count.<\/jats:p>","DOI":"10.1145\/3487554","type":"journal-article","created":{"date-parts":[[2022,9,5]],"date-time":"2022-09-05T08:31:28Z","timestamp":1662366688000},"page":"1-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud"],"prefix":"10.1145","volume":"16","author":[{"given":"Xiang","family":"Li","sequence":"first","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Stanwicks","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Provelengios","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Russell","family":"Tessier","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Holcomb","sequence":"additional","affiliation":[{"name":"University of Massachusetts Amherst, Amherst, MA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,18]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"12","volume-title":"Proceedings of the 22nd National Information Systems Security Conference","author":"Soto Juan","year":"1999","unstructured":"Juan Soto. 1999. Statistical testing of random number generators. In Proceedings of the 22nd National Information Systems Security Conference. NIST Gaithersburg, MD, 12."},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2015.2445336"},{"key":"e_1_3_1_4_2","doi-asserted-by":"crossref","first-page":"72","DOI":"10.1109\/SP.2019.00088","volume-title":"Proceedings of the 2019 IEEE Symposium on Security and Privacy","author":"Meijer Carlo","year":"2019","unstructured":"Carlo Meijer and Bernard Van Gastel. 2019. Self-encrypting deception: Weaknesses in the encryption of solid state drives. In Proceedings of the 2019 IEEE Symposium on Security and Privacy. IEEE, 72\u201387."},{"key":"e_1_3_1_5_2","doi-asserted-by":"crossref","first-page":"267","DOI":"10.46586\/tches.v2018.i3.267-292","article-title":"ES-TRNG: A high-throughput, low-area true random number generator based on edge sampling","author":"Yang Bohan","year":"2018","unstructured":"Bohan Yang, Vladimir Ro\u017eic, Milo\u0161 Grujic, Nele Mentens, and Ingrid Verbauwhede. 2018. ES-TRNG: A high-throughput, low-area true random number generator based on edge sampling. IACR Transactions on Cryptographic Hardware and Embedded Systems 2018, 3 (2018), 267\u2013292.","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"e_1_3_1_6_2","doi-asserted-by":"crossref","first-page":"248","DOI":"10.1109\/FPT.2014.7082786","volume-title":"Proceedings of the 2014 International Conference on Field-Programmable Technology","author":"Yang Xian","year":"2014","unstructured":"Xian Yang and Ray C. C. Cheung. 2014. A complementary architecture for high-speed true random number generator. In Proceedings of the 2014 International Conference on Field-Programmable Technology. IEEE, 248\u2013251."},{"key":"e_1_3_1_7_2","first-page":"17","volume-title":"Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems","author":"Majzoobi Mehrdad","year":"2011","unstructured":"Mehrdad Majzoobi, Farinaz Koushanfar, and Srinivas Devadas. 2011. FPGA-based true random number generation using circuit metastability with adaptive feedback control. In Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems. Springer, 17\u201332."},{"key":"e_1_3_1_8_2","first-page":"218","volume-title":"Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications","author":"Peetermans Adriaan","year":"2019","unstructured":"Adriaan Peetermans, Vladimir Rozic, and Ingrid Verbauwhede. 2019. A highly-portable true random number generator based on coherent sampling. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications. IEEE, 218\u2013224."},{"key":"e_1_3_1_9_2","first-page":"1","volume-title":"Proceedings of the 2018 IEEE 23rd European Test Symposium","author":"Balasch Josep","year":"2018","unstructured":"Josep Balasch, Florent Bernard, Viktor Fischer, Milo\u0161 Gruji\u0107, Marek Laban, Oto Petura, Vladimir Ro\u017ei\u0107, Gerard Van Battum, Ingrid Verbauwhede, Marnix Wakker, and Yang Bohan. 2018. Design and testing methodologies for true random number generators towards industry certification. In Proceedings of the 2018 IEEE 23rd European Test Symposium. IEEE, 1\u201310."},{"key":"e_1_3_1_10_2","first-page":"1","volume-title":"Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip","author":"Gaspar Lubos","year":"2011","unstructured":"Lubos Gaspar, Viktor Fischer, Lilian Bossuet, and Robert Fouquet. 2011. Secure extensions of FPGA soft core processors for symmetric key cryptography. In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip. IEEE, 1\u20138."},{"key":"e_1_3_1_11_2","first-page":"194","volume-title":"Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications","author":"Provelengios George","year":"2019","unstructured":"George Provelengios, Daniel Holcomb, and Russell Tessier. 2019. Characterizing power distribution attacks in multi-user FPGA environments. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications. 194\u2013201."},{"key":"e_1_3_1_12_2","first-page":"45","volume-title":"Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications","author":"Giechaskiel Ilias","year":"2019","unstructured":"Ilias Giechaskiel, Kasper Bonne Rasmussen, and Jakub Szefer. 2019. Measuring long wire leakage with ring oscillators in cloud FPGAs. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications. IEEE, 45\u201350."},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00024"},{"key":"e_1_3_1_14_2","first-page":"233","volume-title":"Proceedings of the 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines","author":"Zeitouni Shaza","year":"2021","unstructured":"Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, Ahmad-Reza Sadeghi, and Nele Mentens. 2021. Trusted configuration in cloud FPGAs. In Proceedings of the 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines. IEEE, 233\u2013241."},{"key":"e_1_3_1_15_2","first-page":"236","volume-title":"Proceedings of the 2020 30th International Conference on Field-Programmable Logic and Applications","author":"Wolfe Pierre-Francois","year":"2020","unstructured":"Pierre-Francois Wolfe, Rushi Patel, Robert Munafo, Mayank Varia, and Martin Herbordt. 2020. Secret sharing MPC on FPGAs in the datacenter. In Proceedings of the 2020 30th International Conference on Field-Programmable Logic and Applications. IEEE, 236\u2013242."},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968292"},{"key":"e_1_3_1_17_2","doi-asserted-by":"crossref","first-page":"425","DOI":"10.1145\/1531542.1531639","volume-title":"Proceedings of the 19th ACM Great Lakes Symposium on VLSI","author":"Maiti Abhranil","year":"2009","unstructured":"Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, and Patrick Schaumont. 2009. Physical unclonable function and true random number generator: A compact and scalable implementation. In Proceedings of the 19th ACM Great Lakes Symposium on VLSI. 425\u2013428."},{"key":"e_1_3_1_18_2","first-page":"1","volume-title":"Proceedings of the 2015 52nd ACM\/IEEE Design Automation Conference","author":"Rozic Vladimir","year":"2015","unstructured":"Vladimir Rozic, Bohan Yang, Wim Dehaene, and Ingrid Verbauwhede. 2015. Highly efficient entropy extraction for true random number generators on FPGAs. In Proceedings of the 2015 52nd ACM\/IEEE Design Automation Conference. IEEE, 1\u20136."},{"key":"e_1_3_1_19_2","doi-asserted-by":"crossref","first-page":"453","DOI":"10.1109\/CSCS.2015.19","volume-title":"Proceedings of the 2015 20th International Conference on Control Systems and Computer Science","author":"De\u00e1k Norbert","year":"2015","unstructured":"Norbert De\u00e1k, Tam\u00e1s Gy\u00f6rfi, Kinga M\u00e1rton, Lucia Vacariu, and Octavian Cret. 2015. Highly efficient true random number generator in FPGA devices using phase-locked loops. In Proceedings of the 2015 20th International Conference on Control Systems and Computer Science. IEEE, 453\u2013458."},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.02.004"},{"key":"e_1_3_1_21_2","first-page":"1","volume-title":"Proceedings of the 2009 International Test Conference","author":"Yamaguchi Takahiro J.","year":"2009","unstructured":"Takahiro J. Yamaguchi, Kiyotaka Ichiyama, Harry X. Hou, and Masahiro Ishida. 2009. A robust method for identifying a deterministic jitter model in a total jitter distribution. In Proceedings of the 2009 International Test Conference. IEEE, 1\u201310."},{"key":"e_1_3_1_22_2","first-page":"1","volume-title":"Proceedings of the 2015 IEEE 33rd VLSI Test Symposium","author":"Xu Li","year":"2015","unstructured":"Li Xu, Yan Duan, and Degang Chen. 2015. A low cost jitter separation and characterization method. In Proceedings of the 2015 IEEE 33rd VLSI Test Symposium. IEEE, 1\u20135."},{"issue":"90","key":"e_1_3_1_23_2","first-page":"102","article-title":"Recommendation for the entropy sources used for random bit generation","volume":"800","author":"Turan Meltem S\u00f6nmez","year":"2018","unstructured":"Meltem S\u00f6nmez Turan, Elaine Barker, John Kelsey, Kerry A. McKay, Mary L. Baish, and Michael Boyle. 2018. Recommendation for the entropy sources used for random bit generation. NIST Special Publication 800, 90B (2018), 102.","journal-title":"NIST Special Publication"},{"key":"e_1_3_1_24_2","unstructured":"Chris Celi. 2019. NIST SP800-90B Entropy Assessment. Retrieved from https:\/\/github.com\/usnistgov\/SP800-90B_EntropyAssessment. Accessed 29 November 2020."},{"key":"e_1_3_1_25_2","volume-title":"A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications","author":"Rukhin Andrew","year":"2010","unstructured":"Andrew Rukhin, Juan Soto, James Nechvatal, Miles Smid, and Elaine Barker. 2010. A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications. Technical Report. National Institute of Standards and Technology."},{"key":"e_1_3_1_26_2","first-page":"231","volume-title":"Proceedings of the International Conference on Field Programmable Logic and Applications","author":"Provelengios George","year":"2020","unstructured":"George Provelengios, Daniel Holcomb, and Russell Tessier. 2020. Power wasting circuits for cloud FPGA attacks. In Proceedings of the International Conference on Field Programmable Logic and Applications. 231\u2013235."},{"key":"e_1_3_1_27_2","first-page":"1","volume-title":"Proceedings of the 2020 International Conference on Electronics, Information, and Communication","author":"Choe Jun-Yeong","year":"2020","unstructured":"Jun-Yeong Choe and Kyung-Wook Shin. 2020. A self-timed ring based TRNG with feedback structure for FPGA implementation. In Proceedings of the 2020 International Conference on Electronics, Information, and Communication. IEEE, 1\u20134."},{"issue":"2","key":"e_1_3_1_28_2","doi-asserted-by":"crossref","first-page":"426","DOI":"10.1587\/transinf.E95.D.426","article-title":"FPGA implementation of metasability-based true random number generator","volume":"95","author":"Hata Hisashi","year":"2012","unstructured":"Hisashi Hata and Shuichi Ichikawa. 2012. FPGA implementation of metasability-based true random number generator. IEICE Transactions on Information and Systems 95, 2 (2012), 426\u2013436.","journal-title":"IEICE Transactions on Information and Systems"},{"key":"e_1_3_1_29_2","article-title":"A novel ultra-compact FPGA-compatible TRNG architecture exploiting latched ring oscillators","author":"Sala Riccardo Della","year":"2022","unstructured":"Riccardo Della Sala, Davide Bellizia, and Giuseppe Scotti. 2022. A novel ultra-compact FPGA-compatible TRNG architecture exploiting latched ring oscillators. IEEE Transactions on Circuits and Systems II: Express Briefs 69, 3 (2022), 1672\u20131676.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"issue":"3","key":"e_1_3_1_30_2","first-page":"570","article-title":"FPGA-based true random number generation using programmable delays in oscillator-rings","volume":"67","author":"Anandakumar N. Nalla","year":"2019","unstructured":"N. Nalla Anandakumar, Somitra Kumar Sanadhya, and Mohammad S. Hashmi. 2019. FPGA-based true random number generation using programmable delays in oscillator-rings. IEEE Transactions on Circuits and Systems II: Express Briefs 67, 3 (2019), 570\u2013574.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3019030"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3487554","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3487554","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:31:20Z","timestamp":1750188680000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3487554"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,1,18]]},"references-count":30,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2023,3,31]]}},"alternative-id":["10.1145\/3487554"],"URL":"https:\/\/doi.org\/10.1145\/3487554","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,1,18]]},"assertion":[{"value":"2021-09-08","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-02-23","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-01-18","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}