{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T14:10:20Z","timestamp":1780668620896,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":98,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,5,30]],"date-time":"2022-05-30T00:00:00Z","timestamp":1653868800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Science Foundation","award":["CNS-1931639"],"award-info":[{"award-number":["CNS-1931639"]}]},{"name":"the Netherlands Organisation for Scientific Research (NWO)","award":["NWA.1215.18.014"],"award-info":[{"award-number":["NWA.1215.18.014"]}]},{"name":"The Australian Research Council Discovery Early Career Award","award":["DE200101577"],"award-info":[{"award-number":["DE200101577"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,5,30]]},"DOI":"10.1145\/3488932.3517415","type":"proceedings-article","created":{"date-parts":[[2022,5,24]],"date-time":"2022-05-24T04:23:26Z","timestamp":1653366206000},"page":"756-770","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":30,"title":["SoK"],"prefix":"10.1145","author":[{"given":"Ileana","family":"Buhan","sequence":"first","affiliation":[{"name":"Radboud University, Nijmegen, Netherlands"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lejla","family":"Batina","sequence":"additional","affiliation":[{"name":"Radboud University, Nijmegen, Netherlands"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuval","family":"Yarom","sequence":"additional","affiliation":[{"name":"University of Adelaide, Adelaide, Australia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Patrick","family":"Schaumont","sequence":"additional","affiliation":[{"name":"Worcester Polytechnic Institute, Worcester, MA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,5,30]]},"reference":[{"key":"e_1_3_2_2_1_1","unstructured":"Aoki Laboratory. 2007. Galois field based AES Verilog design. http:\/\/www.aoki.ecei.tohoku.ac.jp\/crypto\/web\/cores.html. (accessed: 20-Nov-2021).  Aoki Laboratory. 2007. Galois field based AES Verilog design. http:\/\/www.aoki.ecei.tohoku.ac.jp\/crypto\/web\/cores.html. (accessed: 20-Nov-2021)."},{"key":"e_1_3_2_2_2_1","article-title":"SIMON Says: Break Area Records of Block Ciphers on FPGAs","volume":"6","author":"Aysu Aydin","year":"2014","unstructured":"Aydin Aysu , Ege Gulcan , and Patrick Schaumont . 2014 . SIMON Says: Break Area Records of Block Ciphers on FPGAs . IEEE Embed. Syst. Lett. 6 , 2 (2014). Aydin Aysu, Ege Gulcan, and Patrick Schaumont. 2014. SIMON Says: Break Area Records of Block Ciphers on FPGAs. IEEE Embed. Syst. Lett. 6, 2 (2014).","journal-title":"IEEE Embed. Syst. Lett."},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"crossref","unstructured":"Melissa Azouaoui Davide Bellizia Ileana Buhan Nicolas Debande S\u00e9bastien Duval Christophe Giraud \u00c9liane Jaulmes Fran\u00e7ois Koeune Elisabeth Oswald Fran\u00e7ois-Xavier Standaert and Carolyn Whitnall. 2020. A Systematic Appraisal of Side Channel Evaluation Strategies. In SSR.  Melissa Azouaoui Davide Bellizia Ileana Buhan Nicolas Debande S\u00e9bastien Duval Christophe Giraud \u00c9liane Jaulmes Fran\u00e7ois Koeune Elisabeth Oswald Fran\u00e7ois-Xavier Standaert and Carolyn Whitnall. 2020. A Systematic Appraisal of Side Channel Evaluation Strategies. In SSR.","DOI":"10.1007\/978-3-030-64357-7_3"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"crossref","unstructured":"Josep Balasch Sebastian Faust Benedikt Gierlichs and Ingrid Verbauwhede. 2012. Theory and Practice of a Leakage Resilient Masking Scheme. In Asiacrypt.  Josep Balasch Sebastian Faust Benedikt Gierlichs and Ingrid Verbauwhede. 2012. Theory and Practice of a Leakage Resilient Masking Scheme. In Asiacrypt.","DOI":"10.1007\/978-3-642-34961-4_45"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"crossref","unstructured":"Josep Balasch Benedikt Gierlichs Vincent Grosso Oscar Reparaz and Fran\u00e7ois-Xavier Standaert. 2015. On the Cost of Lazy Engineering for Masked Software Implementations. In CARDIS.  Josep Balasch Benedikt Gierlichs Vincent Grosso Oscar Reparaz and Fran\u00e7ois-Xavier Standaert. 2015. On the Cost of Lazy Engineering for Masked Software Implementations. In CARDIS.","DOI":"10.1007\/978-3-319-16763-3_5"},{"key":"e_1_3_2_2_6_1","volume-title":"SoK: Computer-Aided Cryptography","author":"Barbosa Manuel","unstructured":"Manuel Barbosa , Gilles Barthe , Karthikeyan Bhargavan , Bruno Blanchet , Cas Cremers , Kevin Liao , and Bryan Parno . 2021. SoK: Computer-Aided Cryptography . In IEEE SP. Manuel Barbosa, Gilles Barthe, Karthikeyan Bhargavan, Bruno Blanchet, Cas Cremers, Kevin Liao, and Bryan Parno. 2021. SoK: Computer-Aided Cryptography. In IEEE SP."},{"key":"e_1_3_2_2_7_1","volume-title":"Implementation and Verification. TCHES 2021","author":"Barthe Gilles","year":"2021","unstructured":"Gilles Barthe , Marc Gourjon , Benjamin Gr\u00e9goire , Maximilian Orlt , Clara Paglialonga , and Lars Porth . 2021 . Masking in Fine-Grained Leakage Models: Construction , Implementation and Verification. TCHES 2021 , 2 (2021). Gilles Barthe, Marc Gourjon, Benjamin Gr\u00e9goire, Maximilian Orlt, Clara Paglialonga, and Lars Porth. 2021. Masking in Fine-Grained Leakage Models: Construction, Implementation and Verification. TCHES 2021, 2 (2021)."},{"key":"e_1_3_2_2_8_1","doi-asserted-by":"crossref","unstructured":"H. Bassen and G. Smith. 1983. Electric field probes--A review. TAP 31 5 (1983).  H. Bassen and G. Smith. 1983. Electric field probes--A review. TAP 31 5 (1983).","DOI":"10.1109\/TAP.1983.1143126"},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"crossref","unstructured":"Ray Beaulieu Douglas Shors Jason Smith Stefan Treatman-Clark BryanWeeks and Louis Wingers. 2015. The SIMON and SPECK Lightweight Block Ciphers. In DAC.  Ray Beaulieu Douglas Shors Jason Smith Stefan Treatman-Clark BryanWeeks and Louis Wingers. 2015. The SIMON and SPECK Lightweight Block Ciphers. In DAC.","DOI":"10.1145\/2744769.2747946"},{"key":"e_1_3_2_2_10_1","unstructured":"Fabrice Bellard. 2005. QEMU a Fast and Portable Dynamic Translator. In USENIX ATC.  Fabrice Bellard. 2005. QEMU a Fast and Portable Dynamic Translator. In USENIX ATC."},{"key":"e_1_3_2_2_11_1","unstructured":"Daniel J. Bernstein. 2005. Cache-timing attacks on AES. Preprint available at http:\/\/cr.yp.to\/papers.html#cachetiming.  Daniel J. Bernstein. 2005. Cache-timing attacks on AES. Preprint available at http:\/\/cr.yp.to\/papers.html#cachetiming."},{"key":"e_1_3_2_2_12_1","volume-title":"Bernstein and Peter Schwabe","author":"Daniel","year":"2008","unstructured":"Daniel J. Bernstein and Peter Schwabe . 2008 . New AES Software Speed Records. In Indocrypt . Daniel J. Bernstein and Peter Schwabe. 2008. New AES Software Speed Records. In Indocrypt."},{"key":"e_1_3_2_2_13_1","volume-title":"The Making of KECCAK. Cryptologia 38, 1","author":"Bertoni Guido","year":"2014","unstructured":"Guido Bertoni , Joan Daemen , Micha\u00ebl Peeters , and Gilles Van Assche . 2014. The Making of KECCAK. Cryptologia 38, 1 ( 2014 ). Guido Bertoni, Joan Daemen, Micha\u00ebl Peeters, and Gilles Van Assche. 2014. The Making of KECCAK. Cryptologia 38, 1 (2014)."},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"crossref","unstructured":"Guido Bertoni Vittorio Zaccaria Luca Breveglieri Matteo Monchiero and Gianluca Palermo. 2005. AES Power Attack Based on Induced Cache Miss and Countermeasure. In ITCC.  Guido Bertoni Vittorio Zaccaria Luca Breveglieri Matteo Monchiero and Gianluca Palermo. 2005. AES Power Attack Based on Induced Cache Miss and Countermeasure. In ITCC.","DOI":"10.1109\/ITCC.2005.62"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"crossref","unstructured":"Shivam Bhasin Anupam Chattopadhyay Annelie Heuser Dirmanto Jap Stjepan Picek and Ritu Ranjan Shrivastwa. 2020. Mind the Portability: AWarriors Guide through Realistic Profiled Side-channel Analysis. In NDSS.  Shivam Bhasin Anupam Chattopadhyay Annelie Heuser Dirmanto Jap Stjepan Picek and Ritu Ranjan Shrivastwa. 2020. Mind the Portability: AWarriors Guide through Realistic Profiled Side-channel Analysis. In NDSS.","DOI":"10.14722\/ndss.2020.24390"},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"crossref","unstructured":"Beg\u00fcl Bilgin Benedikt Gierlichs Svetla Nikova Ventzislav Nikov and Vincent Rijmen. 2014. Higher-Order Threshold Implementations. In Asiacrypt.  Beg\u00fcl Bilgin Benedikt Gierlichs Svetla Nikova Ventzislav Nikov and Vincent Rijmen. 2014. Higher-Order Threshold Implementations. In Asiacrypt.","DOI":"10.1007\/978-3-662-45608-8_18"},{"key":"e_1_3_2_2_17_1","volume-title":"Wood","author":"Binkert Nathan","year":"2011","unstructured":"Nathan Binkert , Bradford Beckmann , Gabriel Black , Steven K. Reinhardt , Ali Saidi , Arkaprava Basu , Joel Hestness , Derek R. Hower , Tushar Krishna , Somayeh Sardashti , Rathijit Sen , Korey Sewell , Muhammad Shoaib , Nilay Vaish , Mark D. Hill , and David A . Wood . 2011 . The Gem5 Simulator. SIGARCH CAN 39, 2 (2011). Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The Gem5 Simulator. SIGARCH CAN 39, 2 (2011)."},{"key":"e_1_3_2_2_18_1","volume-title":"PRESENT: An Ultra-Lightweight Block Cipher. In CHES.","author":"Bogdanov A.","year":"2007","unstructured":"A. Bogdanov , L. R. Knudsen , G. Leander , C. Paar , A. Poschmann , M. J. B. Robshaw , Y. Seurin , and C. Vikkelsoe . 2007 . PRESENT: An Ultra-Lightweight Block Cipher. In CHES. A. Bogdanov, L. R. Knudsen, G. Leander, C. Paar, A. Poschmann, M. J. B. Robshaw, Y. Seurin, and C. Vikkelsoe. 2007. PRESENT: An Ultra-Lightweight Block Cipher. In CHES."},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"crossref","unstructured":"Billy Bob Brumley and Nicola Tuveri. 2011. Remote Timing Attacks Are Still Practical. In ESORICS.  Billy Bob Brumley and Nicola Tuveri. 2011. Remote Timing Attacks Are Still Practical. In ESORICS.","DOI":"10.1007\/978-3-642-23822-2_20"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"crossref","unstructured":"Robert Locke Callan Alenka G. Zajic and Milos Prvulovic. 2014. A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events. In MICRO.  Robert Locke Callan Alenka G. Zajic and Milos Prvulovic. 2014. A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events. In MICRO.","DOI":"10.1109\/MICRO.2014.39"},{"key":"e_1_3_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/3243734.3243802"},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"crossref","unstructured":"Suresh Chari Charanjit S. Jutla Josyula R. Rao and Pankaj Rohatgi. 1999. Towards Sound Approaches to Counteract Power-Analysis Attacks. In CRYPTO.  Suresh Chari Charanjit S. Jutla Josyula R. Rao and Pankaj Rohatgi. 1999. Towards Sound Approaches to Counteract Power-Analysis Attacks. In CRYPTO.","DOI":"10.1007\/3-540-48405-1_26"},{"key":"e_1_3_2_2_23_1","doi-asserted-by":"crossref","unstructured":"Zhimin Chen and Yujie Zhou. 2006. Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. In CHES.  Zhimin Chen and Yujie Zhou. 2006. Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. In CHES.","DOI":"10.1007\/11894063_20"},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"crossref","unstructured":"Thomas De Cnudde Beg\u00fcl Bilgin Benedikt Gierlichs Ventzislav Nikov Svetla Nikova and Vincent Rijmen. 2017. Does Coupling Affect the Security of Masked Implementations?. In COSADE Sylvain Guilley (Ed.).  Thomas De Cnudde Beg\u00fcl Bilgin Benedikt Gierlichs Ventzislav Nikov Svetla Nikova and Vincent Rijmen. 2017. Does Coupling Affect the Security of Masked Implementations?. In COSADE Sylvain Guilley (Ed.).","DOI":"10.1007\/978-3-319-64647-3_1"},{"key":"e_1_3_2_2_25_1","unstructured":"Jean-S\u00e9bastien Coron. 2014. Higher Order Masking of Look-Up Tables. In Eurocrypt.  Jean-S\u00e9bastien Coron. 2014. Higher Order Masking of Look-Up Tables. In Eurocrypt."},{"key":"e_1_3_2_2_26_1","unstructured":"Jean-S\u00e9bastien Coron Emmanuel Prouff Matthieu Rivain and Thomas Roche. 2014. Higher-Order Side Channel Security and Mask Refreshing. In FSE.  Jean-S\u00e9bastien Coron Emmanuel Prouff Matthieu Rivain and Thomas Roche. 2014. Higher-Order Side Channel Security and Mask Refreshing. In FSE."},{"key":"e_1_3_2_2_27_1","volume-title":"The Design of Rijndael - The Advanced Encryption Standard (AES)","author":"Daemen Joan","unstructured":"Joan Daemen and Vincent Rijmen . 2020. The Design of Rijndael - The Advanced Encryption Standard (AES) , Second Edition. Springer . Joan Daemen and Vincent Rijmen. 2020. The Design of Rijndael - The Advanced Encryption Standard (AES), Second Edition. Springer."},{"key":"e_1_3_2_2_29_1","doi-asserted-by":"crossref","unstructured":"John Demme Robert Martin AdamWaksman and Simha Sethumadhavan. 2012. Side-channel vulnerability factor: A metric for measuring information leakage. In ISCA.  John Demme Robert Martin AdamWaksman and Simha Sethumadhavan. 2012. Side-channel vulnerability factor: A metric for measuring information leakage. In ISCA.","DOI":"10.1109\/ISCA.2012.6237010"},{"key":"e_1_3_2_2_30_1","volume-title":"PINPAS: A Tool for Power Analysis of Smartcards. In SEC.","author":"den Hartog Jerry","year":"2003","unstructured":"Jerry den Hartog , Jan Verschuren , Erik P. de Vink , Jaap de Vos , and W. Wiersma . 2003 . PINPAS: A Tool for Power Analysis of Smartcards. In SEC. Jerry den Hartog, Jan Verschuren, Erik P. de Vink, Jaap de Vos, andW. Wiersma. 2003. PINPAS: A Tool for Power Analysis of Smartcards. In SEC."},{"key":"e_1_3_2_2_31_1","unstructured":"ETH Zurich. [n.d.]. Pulp Platform. https:\/\/pulp-platform.org\/. (accessed: 20-Nov-2021).  ETH Zurich. [n.d.]. Pulp Platform. https:\/\/pulp-platform.org\/. (accessed: 20-Nov-2021)."},{"key":"e_1_3_2_2_32_1","volume-title":"PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance. In HOST.","author":"Vinod Ganesan Muhammad Arsath K. F","year":"2020","unstructured":"Muhammad Arsath K. F , Vinod Ganesan , Rahul Bodduna , and Chester Rebeiro . 2020 . PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance. In HOST. Muhammad Arsath K. F, Vinod Ganesan, Rahul Bodduna, and Chester Rebeiro. 2020. PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance. In HOST."},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jare.2015.02.006"},{"key":"e_1_3_2_2_34_1","volume-title":"The New Millennium Edition: Mainly Electromagnetism and Matter","author":"Feynman R.P.","year":"2011","unstructured":"R.P. Feynman , R.B. Leighton , and M. Sands . 2011 . The Feynman Lectures on Physics , Vol. II : The New Millennium Edition: Mainly Electromagnetism and Matter . Basic Books . R.P. Feynman, R.B. Leighton, and M. Sands. 2011. The Feynman Lectures on Physics, Vol. II: The New Millennium Edition: Mainly Electromagnetism and Matter. Basic Books."},{"key":"e_1_3_2_2_35_1","volume-title":"Gammel","author":"Fischer Wieland","year":"2005","unstructured":"Wieland Fischer and Berndt M . Gammel . 2005 . Masking at Gate Level in the Presence of Glitches. In CHES. Wieland Fischer and Berndt M. Gammel. 2005. Masking at Gate Level in the Presence of Glitches. In CHES."},{"key":"e_1_3_2_2_37_1","volume-title":"Kuhn","author":"Gajski Daniel","year":"1983","unstructured":"Daniel Gajski and Robert H . Kuhn . 1983 . New VLSI Tools - Guest Editors' Introduction. Computer 16, 12 (1983). Daniel Gajski and Robert H. Kuhn. 1983. New VLSI Tools - Guest Editors' Introduction. Computer 16, 12 (1983)."},{"key":"e_1_3_2_2_38_1","doi-asserted-by":"crossref","unstructured":"Neel Gala Arjun Menon Rahul Bodduna G. S. Madhusudan and V. Kamakoti. 2016. SHAKTI Processors: An Open-Source Hardware Initiative. In VLSI Design.  Neel Gala Arjun Menon Rahul Bodduna G. S. Madhusudan and V. Kamakoti. 2016. SHAKTI Processors: An Open-Source Hardware Initiative. In VLSI Design.","DOI":"10.1109\/VLSID.2016.130"},{"key":"e_1_3_2_2_39_1","volume-title":"Electromagnetic Analysis: Concrete Results. In CHES.","author":"Gandolfi Karine","year":"2001","unstructured":"Karine Gandolfi , Christophe Mourtel , and Francis Olivier . 2001 . Electromagnetic Analysis: Concrete Results. In CHES. Karine Gandolfi, Christophe Mourtel, and Francis Olivier. 2001. Electromagnetic Analysis: Concrete Results. In CHES."},{"key":"e_1_3_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-016-0141-6"},{"key":"e_1_3_2_2_42_1","doi-asserted-by":"crossref","unstructured":"Daniel Genkin Adi Shamir and Eran Tromer. 2014. RSA Key Extraction via Low-Bandwidth Acoustic Cryptanalysis. In CRYPTO.  Daniel Genkin Adi Shamir and Eran Tromer. 2014. RSA Key Extraction via Low-Bandwidth Acoustic Cryptanalysis. In CRYPTO.","DOI":"10.1007\/978-3-662-44371-2_25"},{"key":"e_1_3_2_2_43_1","doi-asserted-by":"crossref","unstructured":"Ashrujit Ghoshal and Thomas De Cnudde. 2017. Several Masked Implementations of the Boyar-Peralta AES S-Box. In Indocrypt.  Ashrujit Ghoshal and Thomas De Cnudde. 2017. Several Masked Implementations of the Boyar-Peralta AES S-Box. In Indocrypt.","DOI":"10.1007\/978-3-319-71667-1_20"},{"key":"e_1_3_2_2_44_1","volume-title":"Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs. In USENIX Security.","author":"Gigerl Barbara","year":"2021","unstructured":"Barbara Gigerl , Vedad Hadzic , Robert Primas , Stefan Mangard , and Roderick Bloem . 2021 . Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs. In USENIX Security. Barbara Gigerl, Vedad Hadzic, Robert Primas, Stefan Mangard, and Roderick Bloem. 2021. Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs. In USENIX Security."},{"key":"e_1_3_2_2_45_1","volume-title":"A testing methodology for side channel resistance validation. NIST non-invasive attack testing workshop","author":"Goodwill G.","year":"2018","unstructured":"G. Goodwill , J.J.B. Jun , and P. Rohatgi . 2018. A testing methodology for side channel resistance validation. NIST non-invasive attack testing workshop ( 2018 ). G. Goodwill, J.J.B. Jun, and P.Rohatgi. 2018. A testing methodology for side channel resistance validation. NIST non-invasive attack testing workshop (2018)."},{"key":"e_1_3_2_2_46_1","volume-title":"507270","author":"Grant","year":"2004","unstructured":"Grant agreement ID : 507270 . 2004 . Side Channel Analysis Resistant Design Flow . https:\/\/cordis.europa.eu\/project\/id\/507270. [Online; accessed 20-Nov-2021]. Grant agreement ID: 507270. 2004. Side Channel Analysis Resistant Design Flow. https:\/\/cordis.europa.eu\/project\/id\/507270. [Online; accessed 20-Nov-2021]."},{"key":"e_1_3_2_2_47_1","doi-asserted-by":"crossref","unstructured":"Hannes Gross Stefan Mangard and Thomas Korak. 2016. Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order. In TIS.  Hannes Gross Stefan Mangard and Thomas Korak. 2016. Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order. In TIS.","DOI":"10.1145\/2996366.2996426"},{"key":"e_1_3_2_2_48_1","doi-asserted-by":"crossref","unstructured":"Hannes Gro\u00df David Schaffenrath and Stefan Mangard. 2017. Higher-Order Side-Channel Protected Implementations of KECCAK. In DSD.  Hannes Gro\u00df David Schaffenrath and Stefan Mangard. 2017. Higher-Order Side-Channel Protected Implementations of KECCAK. In DSD.","DOI":"10.1109\/DSD.2017.21"},{"key":"e_1_3_2_2_49_1","unstructured":"Miao Tony He Jungmin Park Adib Nahiyan Apostol Vassilev Yier Jin and Mark Mohammad Tehranipoor. 2019. RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level. In VTS.  Miao Tony He Jungmin Park Adib Nahiyan Apostol Vassilev Yier Jin and Mark Mohammad Tehranipoor. 2019. RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level. In VTS."},{"key":"e_1_3_2_2_50_1","volume-title":"AMASIVE: An Adaptable and Modular Autonomous Side-Channel Vulnerability Evaluation Framework.","author":"Huss Sorin A.","year":"2013","unstructured":"Sorin A. Huss , Marc St\u00f6ttinger , and Michael Zohner . 2013 . AMASIVE: An Adaptable and Modular Autonomous Side-Channel Vulnerability Evaluation Framework. Sorin A. Huss, Marc St\u00f6ttinger, and Michael Zohner. 2013. AMASIVE: An Adaptable and Modular Autonomous Side-Channel Vulnerability Evaluation Framework."},{"key":"e_1_3_2_2_51_1","volume-title":"Private Circuits: Securing Hardware against Probing Attacks. In CRYPTO.","author":"Ishai Yuval","year":"2003","unstructured":"Yuval Ishai , Amit Sahai , and David Wagner . 2003 . Private Circuits: Securing Hardware against Probing Attacks. In CRYPTO. Yuval Ishai, Amit Sahai, and David Wagner. 2003. Private Circuits: Securing Hardware against Probing Attacks. In CRYPTO."},{"key":"e_1_3_2_2_52_1","volume-title":"Wagner","author":"Ishai Yuval","year":"2003","unstructured":"Yuval Ishai , Amit Sahai , and David A . Wagner . 2003 . Private Circuits : Securing Hardware against Probing Attacks. In CRYPTO, Dan Boneh (Ed .). Yuval Ishai, Amit Sahai, and David A. Wagner. 2003. Private Circuits: Securing Hardware against Probing Attacks. In CRYPTO, Dan Boneh (Ed.)."},{"key":"e_1_3_2_2_53_1","doi-asserted-by":"crossref","unstructured":"Paul C. Kocher. 1996. Timing Attacks on Implementations of Diffie-Hellman RSA DSS and Other Systems. In CRYPTO.  Paul C. Kocher. 1996. Timing Attacks on Implementations of Diffie-Hellman RSA DSS and Other Systems. In CRYPTO.","DOI":"10.1007\/3-540-68697-5_9"},{"key":"e_1_3_2_2_54_1","doi-asserted-by":"crossref","unstructured":"Paul C. Kocher Joshua Jaffe and Benjamin Jun. 1999. Differential Power Analysis. In CRYPTO.  Paul C. Kocher Joshua Jaffe and Benjamin Jun. 1999. Differential Power Analysis. In CRYPTO.","DOI":"10.1007\/3-540-48405-1_25"},{"key":"e_1_3_2_2_55_1","doi-asserted-by":"crossref","unstructured":"Juliane Kr\u00e4mer Dmitry Nedospasov Alexander Schl\u00f6sser and Jean-Pierre Seifert. 2013. Differential Photonic Emission Analysis. In COSADE.  Juliane Kr\u00e4mer Dmitry Nedospasov Alexander Schl\u00f6sser and Jean-Pierre Seifert. 2013. Differential Photonic Emission Analysis. In COSADE.","DOI":"10.1007\/978-3-642-40026-1_1"},{"key":"e_1_3_2_2_56_1","doi-asserted-by":"crossref","unstructured":"Yann Le Corre Johann Gro\u00dfsch\u00e4dl and Daniel Dinu. 2018. Micro-architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors. In COSADE.  Yann Le Corre Johann Gro\u00dfsch\u00e4dl and Daniel Dinu. 2018. Micro-architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors. In COSADE.","DOI":"10.1007\/978-3-319-89641-0_5"},{"key":"e_1_3_2_2_57_1","volume-title":"PLATYPUS: Software-based Power Side-Channel Attacks on x86","author":"Lipp Moritz","year":"2021","unstructured":"Moritz Lipp , Andreas Kogler , David Oswald , Michael Schwarz , Catherine Easdon , Claudio Canella , and Daniel Gruss . 2021 . PLATYPUS: Software-based Power Side-Channel Attacks on x86 . In IEEE SP. Moritz Lipp, Andreas Kogler, David Oswald, Michael Schwarz, Catherine Easdon, Claudio Canella, and Daniel Gruss. 2021. PLATYPUS: Software-based Power Side-Channel Attacks on x86. In IEEE SP."},{"key":"e_1_3_2_2_58_1","first-page":"14244","article-title":"A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography","volume":"2103","author":"Lou Xiaoxuan","year":"2021","unstructured":"Xiaoxuan Lou , Tianwei Zhang , Jun Jiang , and Yinqian Zhang . 2021 . A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography . CoRR 2103 . 14244 . Xiaoxuan Lou, Tianwei Zhang, Jun Jiang, and Yinqian Zhang. 2021. A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography. CoRR 2103.14244.","journal-title":"CoRR"},{"key":"e_1_3_2_2_59_1","unstructured":"lowRISC contributors. [n.d.]. Open Titan. https:\/\/opentitan.org\/. (accessed: 20-Nov-2021).  lowRISC contributors. [n.d.]. Open Titan. https:\/\/opentitan.org\/. (accessed: 20-Nov-2021)."},{"key":"e_1_3_2_2_60_1","doi-asserted-by":"crossref","unstructured":"Stefan Mangard. 2004. Hardware Countermeasures against DPA -- A Statistical Analysis of Their Effectiveness. In CT-RSA.  Stefan Mangard. 2004. Hardware Countermeasures against DPA -- A Statistical Analysis of Their Effectiveness. In CT-RSA.","DOI":"10.1007\/978-3-540-24660-2_18"},{"key":"e_1_3_2_2_61_1","volume-title":"Gammel","author":"Mangard Stefan","year":"2005","unstructured":"Stefan Mangard , Thomas Popp , and Berndt M . Gammel . 2005 . Side-Channel Leakage of Masked CMOS Gates. In CT-RSA. Stefan Mangard, Thomas Popp, and Berndt M. Gammel. 2005. Side-Channel Leakage of Masked CMOS Gates. In CT-RSA."},{"key":"e_1_3_2_2_62_1","volume-title":"MIRACLE: MIcRo-ArChitectural Leakage Evaluation. Cryptology ePrint Archive, Report 2021\/261.","author":"Marshall Ben","year":"2021","unstructured":"Ben Marshall , Dan Page , and JamesWebb. 2021 . MIRACLE: MIcRo-ArChitectural Leakage Evaluation. Cryptology ePrint Archive, Report 2021\/261. Ben Marshall, Dan Page, and JamesWebb. 2021. MIRACLE: MIcRo-ArChitectural Leakage Evaluation. Cryptology ePrint Archive, Report 2021\/261."},{"key":"e_1_3_2_2_63_1","volume-title":"USENIX Security Symposium.","author":"McCann David","year":"2017","unstructured":"David McCann , Elisabeth Oswald , and Carolyn Whitnall . 2017 . Towards Practical Tools for Side Channel Aware Software Engineering: ?Grey Box' Modelling for Instruction Leakages . In USENIX Security Symposium. David McCann, Elisabeth Oswald, and Carolyn Whitnall. 2017. Towards Practical Tools for Side Channel Aware Software Engineering: ?Grey Box' Modelling for Instruction Leakages. In USENIX Security Symposium."},{"key":"e_1_3_2_2_65_1","doi-asserted-by":"crossref","unstructured":"Thomas S. Messerges. 2000. Securing the AES Finalists Against Power Analysis Attacks. In FSE.  Thomas S. Messerges. 2000. Securing the AES Finalists Against Power Analysis Attacks. In FSE.","DOI":"10.1007\/3-540-44706-7_11"},{"key":"e_1_3_2_2_66_1","volume-title":"Elke De Mulder, and Michael Tunstall","author":"Meyer Lauren De","year":"2020","unstructured":"Lauren De Meyer , Elke De Mulder, and Michael Tunstall . 2020 . On the Effect of the (Micro)Architecture on the Development of Side-Channel Resistant Software. Cryptology ePrint Archive, Report 2020\/1297. Lauren De Meyer, Elke De Mulder, and Michael Tunstall. 2020. On the Effect of the (Micro)Architecture on the Development of Side-Channel Resistant Software. Cryptology ePrint Archive, Report 2020\/1297."},{"key":"e_1_3_2_2_67_1","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2019.i2.256-292"},{"key":"e_1_3_2_2_68_1","volume-title":"Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Mohammad Tehranipoor.","author":"Nahiyan Adib","year":"2020","unstructured":"Adib Nahiyan , Jungmin Park , Miao Tony He , Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Mohammad Tehranipoor. 2020 . SCRIPT : A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation. ACM TODAES 25, 3 (2020). Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, and Mark Mohammad Tehranipoor. 2020. SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation. ACM TODAES 25, 3 (2020)."},{"key":"e_1_3_2_2_69_1","doi-asserted-by":"crossref","unstructured":"Svetla Nikova Christian Rechberger and Vincent Rijmen. 2006. Threshold Implementations Against Side-Channel Attacks and Glitches. In Information and Communications Security.  Svetla Nikova Christian Rechberger and Vincent Rijmen. 2006. Threshold Implementations Against Side-Channel Attacks and Glitches. In Information and Communications Security.","DOI":"10.1007\/11935308_38"},{"key":"e_1_3_2_2_70_1","unstructured":"Colin O'Flynn and Jasper van Woudenberg. 2021. The Hardware Hacking Handbook: Breaking Embedded Security with Hardware Attacks. No Starch Press.  Colin O'Flynn and Jasper van Woudenberg. 2021. The Hardware Hacking Handbook: Breaking Embedded Security with Hardware Attacks. No Starch Press."},{"key":"e_1_3_2_2_72_1","doi-asserted-by":"crossref","unstructured":"Kostas Papagiannopoulos and Nikita Veshchikov. 2017. Mind the Gap: Towards Secure 1st-Order Masking in Software. In COSADE.  Kostas Papagiannopoulos and Nikita Veshchikov. 2017. Mind the Gap: Towards Secure 1st-Order Masking in Software. In COSADE.","DOI":"10.1007\/978-3-319-64647-3_17"},{"key":"e_1_3_2_2_74_1","doi-asserted-by":"crossref","unstructured":"Jean-Jacques Quisquater and David Samyde. 2001. ElectroMagnetic Analysis (EMA): Measures and Counter-measures for Smart Cards. In Smart Card Programming and Security.  Jean-Jacques Quisquater and David Samyde. 2001. ElectroMagnetic Analysis (EMA): Measures and Counter-measures for Smart Cards. In Smart Card Programming and Security.","DOI":"10.1007\/3-540-45418-7_17"},{"key":"e_1_3_2_2_75_1","volume-title":"Low Power Design Essentials","author":"Rabaey Jan M.","unstructured":"Jan M. Rabaey . 2009. Low Power Design Essentials . Springer . Jan M. Rabaey. 2009. Low Power Design Essentials. Springer."},{"key":"e_1_3_2_2_76_1","doi-asserted-by":"crossref","unstructured":"Oscar Reparaz. 2016. Detecting Flawed Masking Schemes with Leakage Detection Tests. In FSE.  Oscar Reparaz. 2016. Detecting Flawed Masking Schemes with Leakage Detection Tests. In FSE.","DOI":"10.1007\/978-3-662-52993-5_11"},{"key":"e_1_3_2_2_77_1","doi-asserted-by":"crossref","unstructured":"Oscar Reparaz Beg\u00fcl Bilgin Svetla Nikova Benedikt Gierlichs and Ingrid Verbauwhede. 2015. Consolidating Masking Schemes. In CRYPTO.  Oscar Reparaz Beg\u00fcl Bilgin Svetla Nikova Benedikt Gierlichs and Ingrid Verbauwhede. 2015. Consolidating Masking Schemes. In CRYPTO.","DOI":"10.1007\/978-3-662-47989-6_37"},{"key":"e_1_3_2_2_78_1","doi-asserted-by":"crossref","unstructured":"Unai Rioja Lejla Batina and Igor Armendariz. 2020. When Similarities Among Devices are Taken for Granted: Another Look at Portability. In Africacrypt.  Unai Rioja Lejla Batina and Igor Armendariz. 2020. When Similarities Among Devices are Taken for Granted: Another Look at Portability. In Africacrypt.","DOI":"10.1007\/978-3-030-51938-4_17"},{"key":"e_1_3_2_2_79_1","volume-title":"https:\/\/www.riscure.com\/security-tools\/inspector-sca. [Online","author":"Inspector","year":"2021","unstructured":"Riscure. 2002. Inspector SCA. https:\/\/www.riscure.com\/security-tools\/inspector-sca. [Online ; accessed 20- Nov- 2021 ]. Riscure. 2002. Inspector SCA. https:\/\/www.riscure.com\/security-tools\/inspector-sca. [Online; accessed 20-Nov-2021]."},{"key":"e_1_3_2_2_80_1","doi-asserted-by":"crossref","unstructured":"Matthieu Rivain and Emmanuel Prouff. 2010. Provably Secure Higher-Order Masking of AES. In CHES.  Matthieu Rivain and Emmanuel Prouff. 2010. Provably Secure Higher-Order Masking of AES. In CHES.","DOI":"10.1007\/978-3-642-15031-9_28"},{"key":"e_1_3_2_2_81_1","volume-title":"https:\/\/www.nongnu.org\/simulavr\/. [Online","author":"Roth Theodore","year":"2021","unstructured":"Theodore Roth and Klaus Rudolph . 2001. Simul AVR. https:\/\/www.nongnu.org\/simulavr\/. [Online ; accessed 20- Nov- 2021 ]. Theodore Roth and Klaus Rudolph. 2001. SimulAVR. https:\/\/www.nongnu.org\/simulavr\/. [Online; accessed 20-Nov-2021]."},{"key":"e_1_3_2_2_82_1","unstructured":"Satoh Lab. 2017. Lookup table based AES Verilog design. http:\/\/satoh.cs.uec.ac.jp\/SAKURA\/hardware\/SAKURA-G.html. (accessed: 20-Nov-2021).  Satoh Lab. 2017. Lookup table based AES Verilog design. http:\/\/satoh.cs.uec.ac.jp\/SAKURA\/hardware\/SAKURA-G.html. (accessed: 20-Nov-2021)."},{"key":"e_1_3_2_2_83_1","volume-title":"Tahoori","author":"Schellenberg Falk","year":"2021","unstructured":"Falk Schellenberg , Dennis R. E. Gnad , Amir Moradi , and Mehdi B . Tahoori . 2021 . An Inside Job: Remote Power Analysis Attacks on FPGAs. IEEE Des. Test 38, 3 (2021). Falk Schellenberg, Dennis R. E. Gnad, Amir Moradi, and Mehdi B. Tahoori. 2021. An Inside Job: Remote Power Analysis Attacks on FPGAs. IEEE Des. Test 38, 3 (2021)."},{"key":"e_1_3_2_2_84_1","doi-asserted-by":"crossref","unstructured":"Kai Schramm and Christof Paar. 2006. Higher Order Masking of the AES. In CT-RSA.  Kai Schramm and Christof Paar. 2006. Higher Order Masking of the AES. In CT-RSA.","DOI":"10.1007\/11605805_14"},{"key":"e_1_3_2_2_85_1","volume-title":"Alenka G. Zajic, and Milos Prvulovic.","author":"Sehatbakhsh Nader","year":"2020","unstructured":"Nader Sehatbakhsh , Baki Berkay Yilmaz , Alenka G. Zajic, and Milos Prvulovic. 2020 . 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In CHES.","DOI":"10.1007\/11545262_26"},{"key":"e_1_3_2_2_92_1","volume-title":"A Digital Design Flow for Secure Integrated Circuits. TCAD 25, 7","author":"Tiri Kris","year":"2006","unstructured":"Kris Tiri and Ingrid Verbauwhede . 2006. A Digital Design Flow for Secure Integrated Circuits. TCAD 25, 7 ( 2006 ). Kris Tiri and Ingrid Verbauwhede. 2006. A Digital Design Flow for Secure Integrated Circuits. TCAD 25, 7 (2006)."},{"key":"e_1_3_2_2_93_1","doi-asserted-by":"crossref","unstructured":"Vivek Tiwari Sharad Malik Andrew Wolfe and Mike Tien-Chien Lee. 1996. Instruction Level Power Analysis and Optimization of Software. In VLSI Design.  Vivek Tiwari Sharad Malik Andrew Wolfe and Mike Tien-Chien Lee. 1996. Instruction Level Power Analysis and Optimization of Software. In VLSI Design.","DOI":"10.1007\/978-1-4613-1453-0_9"},{"key":"e_1_3_2_2_94_1","doi-asserted-by":"crossref","unstructured":"Elena Trichina Tymur Korkishko and Kyung Hee Lee. 2005. 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Supercomput (2021)."},{"key":"e_1_3_2_2_96_1","unstructured":"Vamshi PN. 2019. Hardware-implementation of AES Verilog. https:\/\/github.com\/pnvamshi\/Hardware-Implementation-of-AES-Verilog. (accessed: 20-Nov-2021).  Vamshi PN. 2019. Hardware-implementation of AES Verilog. https:\/\/github.com\/pnvamshi\/Hardware-Implementation-of-AES-Verilog. (accessed: 20-Nov-2021)."},{"key":"e_1_3_2_2_97_1","doi-asserted-by":"crossref","unstructured":"Nikita Veshchikov. 2014. SILK: high level of abstraction leakage simulator for side channel analysis. In PPREW@ACSAC.  Nikita Veshchikov. 2014. SILK: high level of abstraction leakage simulator for side channel analysis. In PPREW@ACSAC.","DOI":"10.1145\/2689702.2689706"},{"key":"e_1_3_2_2_98_1","doi-asserted-by":"crossref","unstructured":"Nikita Veshchikov and Sylvain Guilley. 2017. Use of Simulators for Side-Channel Analysis. In EuroS&P Workshops.  Nikita Veshchikov and Sylvain Guilley. 2017. Use of Simulators for Side-Channel Analysis. In EuroS&P Workshops.","DOI":"10.1109\/EuroSPW.2017.59"},{"key":"e_1_3_2_2_99_1","doi-asserted-by":"crossref","unstructured":"Matthew Walker Sascha Bischoff Stephan Diestelhorst Geoff Merrett and Bashir Al-Hashimi. 2018. Hardware-Validated CPU Performance and Energy Modelling. In ISPASS.  Matthew Walker Sascha Bischoff Stephan Diestelhorst Geoff Merrett and Bashir Al-Hashimi. 2018. Hardware-Validated CPU Performance and Energy Modelling. In ISPASS.","DOI":"10.1109\/ISPASS.2018.00013"},{"key":"e_1_3_2_2_100_1","volume-title":"SLEAK: A Side-Channel Leakage Evaluator and Analysis Kit. Technical Report","author":"Walters Dan","year":"2014","unstructured":"Dan Walters , Andrew Hagen , and Eric Kedaigle . 2014 . SLEAK: A Side-Channel Leakage Evaluator and Analysis Kit. Technical Report . The MITRE Corporation . Dan Walters, Andrew Hagen, and Eric Kedaigle. 2014. SLEAK: A Side-Channel Leakage Evaluator and Analysis Kit. Technical Report. The MITRE Corporation."},{"key":"e_1_3_2_2_101_1","unstructured":".  ."},{"key":"e_1_3_2_2_102_1","doi-asserted-by":"crossref","unstructured":"FelixWegener and Amir Moradi. 2018. A First-Order SCA Resistant AES Without Fresh Randomness. In COSADE.  FelixWegener and Amir Moradi. 2018. A First-Order SCA Resistant AES Without Fresh Randomness. In COSADE.","DOI":"10.1007\/978-3-319-89641-0_14"},{"key":"e_1_3_2_2_103_1","doi-asserted-by":"crossref","unstructured":"Yuan Yao Tarun Kathuria Baris Ege and Patrick Schaumont. 2020. Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level. In HOST.  Yuan Yao Tarun Kathuria Baris Ege and Patrick Schaumont. 2020. Architecture Correlation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level. In HOST.","DOI":"10.1109\/HOST45689.2020.9300271"},{"key":"e_1_3_2_2_104_1","volume-title":"RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms. Sci. China Inf. Sci. 58, 12","author":"Zhang Wentao","year":"2015","unstructured":"Wentao Zhang , Zhenzhen Bao , Dongdai Lin , Vincent Rijmen , Bohan Yang , and Ingrid Verbauwhede . 2015. RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms. Sci. China Inf. Sci. 58, 12 ( 2015 ). Wentao Zhang, Zhenzhen Bao, Dongdai Lin, Vincent Rijmen, Bohan Yang, and Ingrid Verbauwhede. 2015. RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms. Sci. China Inf. Sci. 58, 12 (2015)."}],"event":{"name":"ASIA CCS '22: ACM Asia Conference on Computer and Communications Security","location":"Nagasaki Japan","acronym":"ASIA CCS '22","sponsor":["SIGSAC ACM Special Interest Group on Security, Audit, and Control"]},"container-title":["Proceedings of the 2022 ACM on Asia Conference on Computer and Communications Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3488932.3517415","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3488932.3517415","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:48:30Z","timestamp":1750193310000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3488932.3517415"}},"subtitle":["Design Tools for Side-Channel-Aware Implementations"],"short-title":[],"issued":{"date-parts":[[2022,5,30]]},"references-count":98,"alternative-id":["10.1145\/3488932.3517415","10.1145\/3488932"],"URL":"https:\/\/doi.org\/10.1145\/3488932.3517415","relation":{},"subject":[],"published":{"date-parts":[[2022,5,30]]},"assertion":[{"value":"2022-05-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}