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Embed. Comput. Syst."],"published-print":{"date-parts":[[2022,3,31]]},"abstract":"<jats:p>\n            Hardware Trojans can compromise\n            <jats:bold>System-on-Chip (SoC)<\/jats:bold>\n            performance. Protection schemes implemented to combat these threats cannot guarantee 100% detection rate and may also introduce performance overhead. This paper defines the risk of running a job on an SoC as a function of the misdetection rate of the hardware Trojan detection methods implemented on the cores in the SoC. Given the user-defined deadlines of each job, our goal is to minimize the job-level risk as well as the deadline violation rate for both static and dynamic scheduling scenarios. We assume that there is no relationship between the execution time and risk of a task executed on a core. Our risk-aware scheduling algorithm first calculates the probability of possible task allocations and then uses it to derive the task-level deadlines. Each task is then allocated to the core with minimum risk that satisfies the task-level deadline. In addition, in dynamic scheduling, where multiple jobs are injected randomly, we propose to explicitly operate with a reduced virtual deadline to avoid possible future deadline violations. Simulations on randomly generated graphs show that our static scheduler has no deadline violations and achieves 5.1%\u201317.2% lower job-level risk than the popular\n            <jats:bold>Earliest Time First (ETF)<\/jats:bold>\n            algorithm when the deadline constraint is 1.2\u00d7\u20133.0\u00d7 the makespan of ETF. In the dynamic case, the proposed algorithm achieves a violation rate comparable to that of\n            <jats:bold>Earliest Deadline First (EDF)<\/jats:bold>\n            , an algorithm optimized for dynamic scenarios. Even when the injection rate is high, it outperforms EDF with 8.4%\u201310% lower risk when the deadline is 1.5\u00d7\u20133.0\u00d7 the makespan of ETF.\n          <\/jats:p>","DOI":"10.1145\/3489409","type":"journal-article","created":{"date-parts":[[2022,2,8]],"date-time":"2022-02-08T15:11:51Z","timestamp":1644333111000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Probabilistic Risk-Aware Scheduling with Deadline Constraint for Heterogeneous SoCs"],"prefix":"10.1145","volume":"21","author":[{"given":"Xing","family":"Chen","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, Arizona, USA"}]},{"given":"Umit","family":"Ogras","sequence":"additional","affiliation":[{"name":"University of Wisconsin-Madison, Madison, Wisconsin, USA"}]},{"given":"Chaitali","family":"Chakrabarti","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, Arizona, USA"}]}],"member":"320","published-online":{"date-parts":[[2022,2,8]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2015.07.021"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2019.04.029"},{"issue":"8","key":"e_1_3_1_4_2","first-page":"1248","article-title":"DS3: A system-level domain-specific System-on-Chip simulation framework","volume":"69","author":"Arda Samet E.","year":"2020","unstructured":"Samet E. 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