{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T12:16:06Z","timestamp":1771330566833,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,7,10]],"date-time":"2022-07-10T00:00:00Z","timestamp":1657411200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"NSFC","award":["U21B2030, 61874066, 61720106013, 61934005"],"award-info":[{"award-number":["U21B2030, 61874066, 61720106013, 61934005"]}]},{"name":"National Key R&D Program of China","award":["2019YFA0706100"],"award-info":[{"award-number":["2019YFA0706100"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,7,10]]},"DOI":"10.1145\/3489517.3530576","type":"proceedings-article","created":{"date-parts":[[2022,8,23]],"date-time":"2022-08-23T23:19:29Z","timestamp":1661296769000},"page":"1093-1098","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["YOLoC"],"prefix":"10.1145","author":[{"given":"Yiming","family":"Chen","sequence":"first","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Guodong","family":"Yin","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Zhanhong","family":"Tan","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Mingyen","family":"Lee","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Zekun","family":"Yang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Kaisheng","family":"Ma","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]},{"given":"Xueqing","family":"Li","sequence":"additional","affiliation":[{"name":"Tsinghua University, Beijing, China"}]}],"member":"320","published-online":{"date-parts":[[2022,8,23]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Toronto ON Canada","author":"Jouppi N. P.","year":"2017","unstructured":"N. P. Jouppi et al., \"In-Datacenter Performance Analysis of a Tensor Processing Unit,\" in 2017 ISCA, Toronto ON Canada, Jun. 2017."},{"key":"e_1_3_2_1_2_1","volume-title":"Aug.","author":"Skillman A.","year":"2020","unstructured":"A. Skillman and T. Edso, \"A Technical Overview of Cortex-M55 and Ethos-U55: Arm's Most Capable Processors for Endpoint AI,\" in 2020 HCS, Aug. 2020."},{"key":"e_1_3_2_1_3_1","volume-title":"Feb.","author":"Su J.-W.","year":"2021","unstructured":"J.-W. Su et al., \"16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips,\" in 2021 ISSCC, Feb. 2021."},{"key":"e_1_3_2_1_4_1","volume-title":"ISSCC","author":"Dong Q.","year":"2020","unstructured":"Q. Dong et al., \"15.3 A 351TOPS\/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications,\" in ISSCC 2020."},{"key":"e_1_3_2_1_5_1","volume-title":"USA","author":"Xie S.","year":"2021","unstructured":"S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu, and J. P. Kulkarni, \"16.2 eDRAMCIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing,\" in 2021 ISSCC, San Francisco, CA, USA, Feb. 2021."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11390-016-1608-8"},{"key":"e_1_3_2_1_7_1","volume-title":"Seattle WA USA","author":"Reis D.","year":"2018","unstructured":"D. Reis, M. Niemier, and X. S. Hu, \"Computing in memory with FeFETs,\" in 2018 ISLPED, Seattle WA USA, Jul. 2018."},{"key":"e_1_3_2_1_8_1","volume-title":"USA","author":"Jiang H.","year":"2020","unstructured":"H. Jiang et al., \"A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training,\" in 2020 DAC, San Francisco, CA, USA, Jul. 2020."},{"key":"e_1_3_2_1_9_1","volume-title":"ISSCC","author":"Yue J.","year":"2021","unstructured":"J. Yue et al., \"15.2 A 2.75-to-75.9TOPS\/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating,\" in ISSCC 2021."},{"key":"e_1_3_2_1_10_1","volume-title":"USA","author":"Mo H.","year":"2021","unstructured":"H. Mo et al., \"9.2 A 28nm 12.1TOPS\/W Dual-Mode CNN Processor Using Effective-Weight-Based Convolution and Error-Compensation-Based Prediction,\" in 2021 ISSCC, San Francisco, CA, USA, Feb. 2021."},{"key":"e_1_3_2_1_11_1","volume-title":"USA","author":"He K.","year":"2016","unstructured":"K. He, X. Zhang, S. Ren, and J. Sun, \"Deep Residual Learning for Image Recognition,\" in 2016 CVPR, Las Vegas, NV, USA, Jun. 2016."},{"key":"e_1_3_2_1_12_1","volume-title":"A Systematic DNN Weight Pruning Framework using Alternating Direction Method of Multipliers,\" ArXiv180403294 Cs","author":"Zhang T.","year":"2018","unstructured":"T. Zhang et al., \"A Systematic DNN Weight Pruning Framework using Alternating Direction Method of Multipliers,\" ArXiv180403294 Cs, 2018."},{"key":"e_1_3_2_1_13_1","volume-title":"Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference,\" in 2018 CVPR","author":"Jacob B.","year":"2018","unstructured":"B. Jacob et al., \"Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference,\" in 2018 CVPR, Salt Lake City, UT, Jun. 2018."},{"key":"e_1_3_2_1_14_1","volume-title":"Nov.","author":"Li F.","year":"2016","unstructured":"F. Li, B. Zhang, and B. Liu, \"Ternary Weight Networks,\" ArXiv160504711 Cs, Nov. 2016."},{"key":"e_1_3_2_1_15_1","volume-title":"Mar.","author":"Courbariaux M.","year":"2016","unstructured":"M. Courbariaux, I. Hubara, D. Soudry, R. El-Yaniv, and Y. Bengio, \"Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1,\" ArXiv160202830 Cs, Mar. 2016."},{"key":"e_1_3_2_1_16_1","volume-title":"Apr.","author":"Howard A. G.","year":"2017","unstructured":"A. G. Howard et al., \"MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications,\" ArXiv170404861 Cs, Apr. 2017."},{"key":"e_1_3_2_1_17_1","volume-title":"ON","author":"Womg A.","year":"2018","unstructured":"A. Womg, M. J. Shafiee, F. Li, and B. Chwyl, \"Tiny SSD: A Tiny Single-Shot Detection Deep Convolutional Neural Network for Real-Time Embedded Object Detection,\" in 2018 15th Conference on Computer and Robot Vision (CRV), Toronto, ON, Canada, May 2018."},{"issue":"11","key":"e_1_3_2_1_18_1","volume":"54","author":"Pan Y.","year":"2018","unstructured":"Y. Pan et al., \"A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network,\" IEEE Trans. Magn., vol. 54, no. 11, Nov. 2018.","journal-title":"IEEE Trans. Magn."},{"key":"e_1_3_2_1_19_1","volume-title":"A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors,\" IEEE JSSC","author":"Si X.","unstructured":"X. Si et al., \"A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors,\" IEEE JSSC vol. 55, no. 1, Jan. 2020."},{"key":"e_1_3_2_1_20_1","volume-title":"Solid-State Circuits","volume":"54","author":"Biswas A.","unstructured":"A. Biswas and A. P. Chandrakasan, \"CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks,\" IEEE J. Solid-State Circuits, vol. 54, no. 1, Jan. 2019."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928043"},{"key":"e_1_3_2_1_22_1","volume-title":"Dec.","author":"Vinyals O.","year":"2017","unstructured":"O. Vinyals, C. Blundell, T. Lillicrap, K. Kavukcuoglu, and D. Wierstra, \"Matching Networks for One Shot Learning,\" ArXiv160604080 Cs Stat, Dec. 2017."},{"key":"e_1_3_2_1_23_1","volume-title":"Sep.","author":"Szegedy C.","year":"2014","unstructured":"C. Szegedy et al., \"Going Deeper with Convolutions,\" ArXiv14094842 Cs, Sep. 2014."},{"issue":"7","key":"e_1_3_2_1_24_1","volume":"23","author":"Jouppi N. P.","year":"2015","unstructured":"N. P. Jouppi, A. B. Kahng, N. Muralimanohar, and V. Srinivas, \"CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models,\" IEEE Trans. Very Large Scale Integr. VLSI Syst., vol. 23, no. 7, Jul. 2015.","journal-title":"\"CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models,\" IEEE Trans. Very Large Scale Integr. VLSI Syst."},{"key":"e_1_3_2_1_25_1","volume-title":"A 1.17-pJ\/b, 25-Gb\/s\/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator,\" IEEE JSSC","author":"Poulton J. W.","unstructured":"J. W. Poulton et al., \"A 1.17-pJ\/b, 25-Gb\/s\/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator,\" IEEE JSSC, vol. 54, no. 1, Jan. 2019."}],"event":{"name":"DAC '22: 59th ACM\/IEEE Design Automation Conference","location":"San Francisco California","acronym":"DAC '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA"]},"container-title":["Proceedings of the 59th ACM\/IEEE Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3489517.3530576","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3489517.3530576","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:18Z","timestamp":1750186938000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3489517.3530576"}},"subtitle":["deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip"],"short-title":[],"issued":{"date-parts":[[2022,7,10]]},"references-count":25,"alternative-id":["10.1145\/3489517.3530576","10.1145\/3489517"],"URL":"https:\/\/doi.org\/10.1145\/3489517.3530576","relation":{},"subject":[],"published":{"date-parts":[[2022,7,10]]},"assertion":[{"value":"2022-08-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}