{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,4]],"date-time":"2026-04-04T03:30:50Z","timestamp":1775273450190,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":9,"publisher":"ACM","license":[{"start":{"date-parts":[[2021,9,24]],"date-time":"2021-09-24T00:00:00Z","timestamp":1632441600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2021,9,24]]},"DOI":"10.1145\/3490700.3490715","type":"proceedings-article","created":{"date-parts":[[2022,1,6]],"date-time":"2022-01-06T00:15:54Z","timestamp":1641428154000},"page":"88-93","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Comprehensive Review on the Runtime of NVidia Deep Learning Accelerator"],"prefix":"10.1145","author":[{"given":"Xu","family":"Lyu","sequence":"first","affiliation":[{"name":"Information Engineering College, Capital Normal University, China"}]},{"given":"Weigong","family":"Zhang","sequence":"additional","affiliation":[{"name":"Information Engineering College, Capital Normal University, China"}]},{"given":"Junwen","family":"Wang","sequence":"additional","affiliation":[{"name":"Information Engineering College, Capital Normal University, China"}]}],"member":"320","published-online":{"date-parts":[[2022,1,5]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Integrating NVIDIA deep learning accelerator (NVDLA) with RISC-V SoC on FireSim. arXiv","author":"Farshchi Farzad","year":"2019","unstructured":"Farzad Farshchi , Qijing Huang , and Heechul Yun . 2019. Integrating NVIDIA deep learning accelerator (NVDLA) with RISC-V SoC on FireSim. arXiv ( 2019 ). Farzad Farshchi, Qijing Huang, and Heechul Yun. 2019. Integrating NVIDIA deep learning accelerator (NVDLA) with RISC-V SoC on FireSim. arXiv (2019)."},{"key":"e_1_3_2_1_2_1","volume-title":"Workshop on Computer Architecture Research with RISC-V (CARRV).","author":"Giri D","year":"2020","unstructured":"D Giri , K L Chiu , G Eichler , P Mantovani , and ... 2020 . Ariane+ NVDLA: Seamless Third-Party IP Integration with ESP . In Workshop on Computer Architecture Research with RISC-V (CARRV). D Giri, K L Chiu, G Eichler, P Mantovani, and ... 2020. Ariane+ NVDLA: Seamless Third-Party IP Integration with ESP. In Workshop on Computer Architecture Research with RISC-V (CARRV)."},{"key":"e_1_3_2_1_3_1","volume-title":"flatbuffers. Retrieved","year":"2021","unstructured":"Google. flatbuffers. Retrieved July 23, 2021 from https:\/\/google.github.io\/flatbuffers\/ Google. flatbuffers. Retrieved July 23, 2021 from https:\/\/google.github.io\/flatbuffers\/"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2019.8741778"},{"key":"e_1_3_2_1_6_1","volume-title":"Retrieved","author":"NVIDIA.","year":"2018","unstructured":"NVIDIA. 2018 . NVDLA Primer \u2014 NVDLA Documentation . Retrieved November 20, 2020 from http:\/\/nvdla.org\/primer.html NVIDIA. 2018. NVDLA Primer \u2014 NVDLA Documentation. Retrieved November 20, 2020 from http:\/\/nvdla.org\/primer.html"},{"key":"e_1_3_2_1_7_1","volume-title":"Retrieved","author":"NVIDIA.","year":"2018","unstructured":"NVIDIA. 2018 . Hardware Architectural Specification \u2014 NVDLA Documentation . Retrieved December 17, 2019 from http:\/\/nvdla.org\/hw\/v1\/hwarch.html NVIDIA. 2018. Hardware Architectural Specification \u2014 NVDLA Documentation. Retrieved December 17, 2019 from http:\/\/nvdla.org\/hw\/v1\/hwarch.html"},{"key":"e_1_3_2_1_8_1","unstructured":"Xilinx. Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891).  Xilinx. Zynq UltraScale+ MPSoC Data Sheet: Overview (DS891)."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00716"}],"event":{"name":"ICACS '21: 2021 The 5th International Conference on Algorithms, Computing and Systems","location":"Xi'an China","acronym":"ICACS '21"},"container-title":["2021 The 5th International Conference on Algorithms, Computing and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3490700.3490715","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3490700.3490715","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:30:30Z","timestamp":1750188630000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3490700.3490715"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,24]]},"references-count":9,"alternative-id":["10.1145\/3490700.3490715","10.1145\/3490700"],"URL":"https:\/\/doi.org\/10.1145\/3490700.3490715","relation":{},"subject":[],"published":{"date-parts":[[2021,9,24]]},"assertion":[{"value":"2022-01-05","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}