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Syst."],"published-print":{"date-parts":[[2022,7,31]]},"abstract":"<jats:p>\n            Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of\n            <jats:bold>high-level synthesis (HLS)<\/jats:bold>\n            , accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an\n            <jats:bold>\n              automated DSE framework\u2014\n              <jats:italic>AutoDSE<\/jats:italic>\n            <\/jats:bold>\n            \u2014that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point.\n            <jats:italic>AutoDSE<\/jats:italic>\n            detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that\n            <jats:italic>AutoDSE<\/jats:italic>\n            is able to identify the design point that achieves, on the geometric mean, 19.9\u00d7 speedup over one CPU core for MachSuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries,\n            <jats:italic>AutoDSE<\/jats:italic>\n            can reduce their optimization pragmas by 26.38\u00d7 while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.\n          <\/jats:p>","DOI":"10.1145\/3494534","type":"journal-article","created":{"date-parts":[[2022,2,12]],"date-time":"2022-02-12T12:31:27Z","timestamp":1644669087000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":78,"title":["AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators"],"prefix":"10.1145","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1156-3306","authenticated-orcid":false,"given":"Atefeh","family":"Sohrabizadeh","sequence":"first","affiliation":[{"name":"Computer Science Department, University of California, Los Angeles, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cody Hao","family":"Yu","sequence":"additional","affiliation":[{"name":"Computer Science Department, University of California, Los Angeles, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Min","family":"Gao","sequence":"additional","affiliation":[{"name":"Falcon-computing Inc., CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jason","family":"Cong","sequence":"additional","affiliation":[{"name":"Computer Science Department, University of California, Los Angeles, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,2,12]]},"reference":[{"key":"e_1_3_3_2_2","unstructured":"[n.d.]. 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