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Code Optim."],"published-print":{"date-parts":[[2022,6,30]]},"abstract":"<jats:p>Specialized accelerators deliver orders of a magnitude of higher performance than general-purpose processors. The ever-changing nature of modern workloads is pushing the adoption of Field Programmable Gate Arrays (FPGAs) as the substrate of choice. However, FPGAs are hard to program directly using Hardware Description Languages (HDLs). Even modern high-level HDLs, e.g., Spatial and Chisel, still require hardware expertise.<\/jats:p>\n          <jats:p>This article adopts functional programming concepts to provide a hardware-agnostic higher-level programming abstraction. During synthesis, these abstractions are mechanically lowered into a functional Intermediate Representation (IR) that defines a specific hardware design point. This novel IR expresses different forms of parallelism and standard memory features such as asynchronous off-chip memories or synchronous on-chip buffers. Exposing such features at the IR level is essential for achieving high performance.<\/jats:p>\n          <jats:p>The viability of this approach is demonstrated on two stencil computations and by exploring the optimization space of matrix-matrix multiplication. Starting from a high-level representation for these algorithms, our compiler produces low-level VHSIC Hardware Description Language (VHDL) code automatically. Several design points are evaluated on an Intel Arria\u00a010 FPGA, demonstrating the ability of the IR to exploit different hardware features. This article also shows that the designs produced are competitive with highly tuned OpenCL implementations and outperform hardware-agnostic OpenCL code.<\/jats:p>","DOI":"10.1145\/3501768","type":"journal-article","created":{"date-parts":[[2022,1,31]],"date-time":"2022-01-31T13:43:02Z","timestamp":1643636582000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3835-4774","authenticated-orcid":false,"given":"Christof","family":"Schlaak","sequence":"first","affiliation":[{"name":"University of Edinburgh, United Kingdom"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1629-8617","authenticated-orcid":false,"given":"Tzung-Han","family":"Juang","sequence":"additional","affiliation":[{"name":"McGill University, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4811-2469","authenticated-orcid":false,"given":"Christophe","family":"Dubach","sequence":"additional","affiliation":[{"name":"McGill University, Canada"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,1,31]]},"reference":[{"key":"e_1_3_3_2_2","volume-title":"Digital Circuit in C \\lambda aSH: Functional Specifications and Type-Directed Synthesis","author":"Baaij C. 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