{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:47:56Z","timestamp":1773193676176,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":123,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,2,22]],"date-time":"2022-02-22T00:00:00Z","timestamp":1645488000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,2,28]]},"DOI":"10.1145\/3503222.3507745","type":"proceedings-article","created":{"date-parts":[[2022,2,22]],"date-time":"2022-02-22T20:49:01Z","timestamp":1645562941000},"page":"300-313","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":29,"title":["CRISP: critical slice prefetching"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5181-9639","authenticated-orcid":false,"given":"Heiner","family":"Litz","sequence":"first","affiliation":[{"name":"University of California at Santa Cruz, USA"}]},{"given":"Grant","family":"Ayers","sequence":"additional","affiliation":[{"name":"Google, USA"}]},{"given":"Parthasarathy","family":"Ranganathan","sequence":"additional","affiliation":[{"name":"Google, USA"}]}],"member":"320","published-online":{"date-parts":[[2022,2,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304062"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00066"},{"key":"e_1_3_2_1_3_1","volume-title":"Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA). 424\u2013434","author":"Alipour Mehdi","year":"2020","unstructured":"Mehdi Alipour, Stefanos Kaxiras, David Black-Schaffer, and Rakesh Kumar. 2020. Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA). 424\u2013434."},{"key":"e_1_3_2_1_4_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). 716\u2013721","author":"Alipour Mehdi","year":"2019","unstructured":"Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, and David Black-Schaffer. 2019. Fiforder microarchitecture: Ready-aware instruction scheduling for ooo processors. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). 716\u2013721."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358293"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378498"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322234"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00021"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00053"},{"key":"e_1_3_2_1_10_1","volume-title":"International Workshop on Power-Aware Computer Systems. 180\u2013195","author":"Balasubramonian Rajeev","year":"2003","unstructured":"Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, and Alper Buyuktosunoglu. 2003. Hot-and-cold: Using criticality in the design of energy-efficient caches. In International Workshop on Power-Aware Computer Systems. 180\u2013195."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00018"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358325"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/59287.59291"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.29469"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/1989323.1989438"},{"key":"e_1_3_2_1_16_1","volume-title":"International Workshop on AI-assisted Design for Architecture (AIDArc), held in conjunction with ISCA.","author":"Braun Peter","year":"2019","unstructured":"Peter Braun and Heiner Litz. 2019. Understanding memory access patterns for prefetching. In International Workshop on AI-assisted Design for Architecture (AIDArc), held in conjunction with ISCA."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2003.1191551"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/144965.144974"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750407"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/300979.300995"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/2854038.2854044"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991128"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379248"},{"key":"e_1_3_2_1_25_1","unstructured":"Intel Corparation. 2016. Intel (R) 64 and IA-32 Architectures Software Developer\u2019s Manual. Combined Volumes Dec."},{"key":"e_1_3_2_1_26_1","volume-title":"13th $USENIX$ Symposium on Operating Systems Design and Implementation ($OSDI$ 18). 17\u201332.","author":"Cui Weidong","unstructured":"Weidong Cui, Xinyang Ge, Baris Kasikci, Ben Niu, Upamanyu Sharma, Ruoyu Wang, and Insu Yun. 2018. $REPT$: Reverse Debugging of Failures in Deployed Software. In 13th $USENIX$ Symposium on Operating Systems Design and Implementation ($OSDI$ 18). 17\u201332."},{"key":"e_1_3_2_1_27_1","unstructured":"Ian Cutress. 2019. Examining Intel\u2019s Ice Lake Processors: Taking a Bite of the Sunny Cove Microarchitecture."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","unstructured":"Fredrik Dahlgren and Per Stenstrom. 1995. Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.. In hpca. 68\u201377.","DOI":"10.1109\/HPCA.1995.386554"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480115"},{"key":"e_1_3_2_1_31_1","volume-title":"Julius Mandelblat, Anirudha Rahatekar, Lihu Rappoport, Efraim Rotem, Ahmad Yasin, and Adi Yoaz.","author":"Doweck Jack","year":"2017","unstructured":"Jack Doweck, Wen-Fu Kao, Allen Kuan-yu Lu, Julius Mandelblat, Anirudha Rahatekar, Lihu Rappoport, Efraim Rotem, Ahmad Yasin, and Adi Yoaz. 2017. Inside 6th-generation intel core: New microarchitecture code-named skylake. IEEE Micro."},{"key":"e_1_3_2_1_32_1","unstructured":"Travis Downs. [n.d.]. Gathering Intel on Intel AVX-512 Transitions. https:\/\/travisdowns.github.io\/blog\/2020\/01\/17\/avxfreq1.html"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263597"},{"key":"e_1_3_2_1_34_1","volume-title":"Simultaneous multithreading: A platform for next-generation processors","author":"Eggers Susan J","year":"1997","unstructured":"Susan J Eggers, Joel S Emer, Henry M Levy, Jack L Lo, Rebecca L Stamm, and Dean M Tullsen. 1997. Simultaneous multithreading: A platform for next-generation processors. IEEE micro, 17, 5 (1997), 12\u201319."},{"key":"e_1_3_2_1_35_1","volume-title":"Bulldog: A compiler for VLIW architectures. Yale Univ.","author":"Ellis John R","year":"1985","unstructured":"John R Ellis. 1985. Bulldog: A compiler for VLIW architectures. Yale Univ., New Haven, CT (USA)."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.668985"},{"key":"e_1_3_2_1_37_1","volume-title":"1st JILP Data Prefetching Championship, 29","author":"Ferdman Michael","year":"2009","unstructured":"Michael Ferdman, Stephen Somogyi, and Babak Falsafi. 2009. Spatial memory streaming with rotated patterns. 1st JILP Data Prefetching Championship, 29 (2009)."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003561"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/800046.801649"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1999.808593"},{"key":"e_1_3_2_1_41_1","first-page":"110","article-title":"Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs","volume":"93","author":"Fog Agner","year":"2011","unstructured":"Agner Fog. 2011. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs. Copenhagen University College of Engineering, 93 (2011), 110.","journal-title":"Copenhagen University College of Engineering"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485930"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746228"},{"key":"e_1_3_2_1_44_1","unstructured":"Google. [n.d.]. Propeller: Profile Guided Optimizing Large Scale LLVM-based Relinker. https:\/\/github.com\/google\/llvm-propeller"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/3409963.3410488"},{"key":"e_1_3_2_1_46_1","volume-title":"27th $USENIX$ Security Symposium ($USENIX$ Security 18). 955\u2013972.","author":"Gras Ben","unstructured":"Ben Gras, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2018. Translation leak-aside buffer: Defeating cache side-channel protections with $TLB$ attacks. In 27th $USENIX$ Security Symposium ($USENIX$ Security 18). 955\u2013972."},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446726"},{"key":"e_1_3_2_1_48_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783764"},{"key":"e_1_3_2_1_49_1","unstructured":"Milad Hashemi Kevin Swersky Jamie A Smith Grant Ayers Heiner Litz Jichuan Chang Christos Kozyrakis and Parthasarathy Ranganathan. 2018. Learning memory access patterns. arXiv preprint arXiv:1803.02329."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/1186736.1186737"},{"key":"e_1_3_2_1_51_1","unstructured":"HPS. [n.d.]. Scarab. https:\/\/github.com\/hpsresearchgroup\/scarab"},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.32"},{"key":"e_1_3_2_1_53_1","first-page":"1","article-title":"Access map pattern matching for high performance data cache prefetch","volume":"13","author":"Ishii Yasuo","year":"2011","unstructured":"Yasuo Ishii, Mary Inaba, and Kei Hiraki. 2011. Access map pattern matching for high performance data cache prefetch. Journal of Instruction-Level Parallelism, 13 (2011), 1\u201324.","journal-title":"Journal of Instruction-Level Parallelism"},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540730"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264207"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750392"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"crossref","unstructured":"Harshad Kasture and Daniel Sanchez. 2016. TailBench: A benchmark suite and evaluation methodology for latency-critical applications. In Workload Characterization (IISWC).","DOI":"10.1109\/IISWC.2016.7581261"},{"key":"e_1_3_2_1_58_1","volume-title":"Twig: Profile-Guided BTB Prefetching for Data Center Applications. In MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture. 816\u2013829","author":"Khan Tanvir Ahmed","year":"2021","unstructured":"Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subramoney, Gilles A Pokam, Heiner Litz, and Baris Kasikci. 2021. Twig: Profile-Guided BTB Prefetching for Data Center Applications. In MICRO-54: 54th Annual IEEE\/ACM International Symposium on Microarchitecture. 816\u2013829."},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00024"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00063"},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783763"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1145\/3093336.3037701"},{"key":"e_1_3_2_1_63_1","volume-title":"Ramulator: A fast and extensible DRAM simulator","author":"Kim Yoongu","year":"2015","unstructured":"Yoongu Kim, Weikun Yang, and Onur Mutlu. 2015. Ramulator: A fast and extensible DRAM simulator. IEEE Computer architecture letters, 15, 1 (2015), 45\u201349."},{"key":"e_1_3_2_1_64_1","first-page":"2015","volume-title":"Tracing Summit","author":"Kleen Andi","year":"2015","unstructured":"Andi Kleen and Beeman Strong. 2015. Intel processor trace on linux. Tracing Summit, 2015 (2015)."},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00009"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/3410463.3414629"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302516.3307358"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545223"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"crossref","first-page":"1309","DOI":"10.1109\/TPDS.2008.224","article-title":"Prefetching with helper threads for loosely coupled multiprocessor systems","volume":"20","author":"Lee Jaejin","year":"2008","unstructured":"Jaejin Lee, Changhee Jung, Daeseob Lim, and Yan Solihin. 2008. Prefetching with helper threads for loosely coupled multiprocessor systems. IEEE Transactions on Parallel and Distributed Systems, 20, 9 (2008), 1309\u20131324.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"crossref","unstructured":"Johnny KF Lee and Alan Jay Smith. 1984. Branch prediction strategies and branch target buffer design. Computer 6\u201322.","DOI":"10.1109\/MC.1984.1658927"},{"key":"e_1_3_2_1_72_1","volume-title":"Meltdown: Reading kernel memory from user space. In 27th $USENIX$ Security Symposium ($USENIX$ Security 18). 973\u2013990.","author":"Lipp Moritz","year":"2018","unstructured":"Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, and Daniel Genkin. 2018. Meltdown: Reading kernel memory from user space. In 27th $USENIX$ Security Symposium ($USENIX$ Security 18). 973\u2013990."},{"key":"e_1_3_2_1_73_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2005.18"},{"key":"e_1_3_2_1_74_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379250"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944875"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446087"},{"key":"e_1_3_2_1_77_1","doi-asserted-by":"publisher","DOI":"10.1145\/2786572.2786593"},{"key":"e_1_3_2_1_78_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-018-0611-9"},{"key":"e_1_3_2_1_79_1","doi-asserted-by":"publisher","DOI":"10.5555\/645988.674168"},{"key":"e_1_3_2_1_80_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283861"},{"key":"e_1_3_2_1_81_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176238"},{"key":"e_1_3_2_1_82_1","doi-asserted-by":"publisher","DOI":"10.1145\/1080695.1070000"},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.5555\/1116644.1116665"},{"key":"e_1_3_2_1_84_1","volume-title":"Runahead execution: An effective alternative to large instruction windows","author":"Mutlu Onur","unstructured":"Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N Patt. 2003. Runahead execution: An effective alternative to large instruction windows. IEEE Micro."},{"key":"e_1_3_2_1_85_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00040"},{"key":"e_1_3_2_1_86_1","volume-title":"IEE Proceedings-. 96\u201396","author":"Nesbit Kyle J","year":"2004","unstructured":"Kyle J Nesbit and James E Smith. 2004. Data cache prefetching using a global history buffer. In Software, IEE Proceedings-. 96\u201396."},{"key":"e_1_3_2_1_87_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00019"},{"key":"e_1_3_2_1_88_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2019.8661201"},{"key":"e_1_3_2_1_89_1","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.33"},{"key":"e_1_3_2_1_90_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.10"},{"key":"e_1_3_2_1_91_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598112"},{"key":"e_1_3_2_1_92_1","volume-title":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No. 02CH37315)","author":"Preston Ronald P","year":"2002","unstructured":"Ronald P Preston, Roy W Badeau, Daniel W Bailey, Shane L Bell, Larry L Biro, William J Bowhill, Daniel E Dever, Stephen Felix, Richard Gammack, and Valeria Germini. 2002. Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading. In 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No. 02CH37315). 1, 334\u2013472."},{"key":"e_1_3_2_1_93_1","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480053"},{"key":"e_1_3_2_1_94_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835971"},{"key":"e_1_3_2_1_95_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658635"},{"key":"e_1_3_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.5555\/320080.320085"},{"key":"e_1_3_2_1_97_1","doi-asserted-by":"publisher","DOI":"10.1109\/12.919279"},{"key":"e_1_3_2_1_98_1","volume-title":"Google-wide profiling: A continuous profiling infrastructure for data centers","author":"Ren Gang","unstructured":"Gang Ren, Eric Tune, Tipp Moseley, Yixin Shi, Silvius Rus, and Robert Hundt. 2010. Google-wide profiling: A continuous profiling infrastructure for data centers. IEEE Micro."},{"key":"e_1_3_2_1_99_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1183943"},{"key":"e_1_3_2_1_100_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273440.1250704"},{"key":"e_1_3_2_1_101_1","doi-asserted-by":"crossref","unstructured":"Robert Sch\u00f6ne Thomas Ilsche Mario Bielert Andreas Gocht and Daniel Hackenberg. 2019. Energy efficiency features of the intel skylake-sp processor and their impact on performance. arXiv preprint arXiv:1905.12468.","DOI":"10.1109\/HPCS48598.2019.9188239"},{"key":"e_1_3_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830815"},{"key":"e_1_3_2_1_103_1","article-title":"A case for (partially)-tagged geometric history length predictors","author":"Seznec Andr\u00e9","year":"2006","unstructured":"Andr\u00e9 Seznec. 2006. A case for (partially)-tagged geometric history length predictors. Journal of InstructionLevel Parallelism.","journal-title":"Journal of InstructionLevel Parallelism."},{"key":"e_1_3_2_1_104_1","unstructured":"Harsh Sharangpani. 1999. Intel\u00ae Itanium\u2122 processor microarchitecture overview. In Microprocessor Forum. 10."},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830793"},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.35"},{"key":"e_1_3_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2014.2376112"},{"key":"e_1_3_2_1_108_1","doi-asserted-by":"crossref","unstructured":"Alan Jay Smith. 1978. Sequential program prefetching in memory hierarchies. Computer 7\u201321.","DOI":"10.1109\/C-M.1978.218016"},{"key":"e_1_3_2_1_109_1","doi-asserted-by":"crossref","unstructured":"James E Smith. 1998. A study of branch prediction strategies. In 25 years of the international symposia on Computer architecture (selected papers). 202\u2013215.","DOI":"10.1145\/285930.285980"},{"key":"e_1_3_2_1_110_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003576"},{"key":"e_1_3_2_1_111_1","doi-asserted-by":"publisher","DOI":"10.1145\/1150019.1136508"},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379258"},{"key":"e_1_3_2_1_113_1","doi-asserted-by":"publisher","DOI":"10.5555\/290940.290973"},{"key":"e_1_3_2_1_114_1","doi-asserted-by":"publisher","DOI":"10.5555\/266800.266804"},{"key":"e_1_3_2_1_115_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798280"},{"key":"e_1_3_2_1_116_1","volume-title":"An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of research and Development, 11, 1","author":"Tomasulo Robert M","year":"1967","unstructured":"Robert M Tomasulo. 1967. An efficient algorithm for exploiting multiple arithmetic units. IBM Journal of research and Development, 11, 1 (1967), 25\u201333."},{"key":"e_1_3_2_1_117_1","doi-asserted-by":"publisher","DOI":"10.1145\/1037187.1024411"},{"key":"e_1_3_2_1_118_1","unstructured":"Vincent M Weaver. 2016. Advanced hardware profiling and sampling (PEBS IBS etc.): creating a new PAPI sampling interface. Tech. rep. UMAINEVMW-TR-PEBS-IBS-SAMPLING-2016-08. http:\/\/web. eece. maine \u2026."},{"key":"e_1_3_2_1_119_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798239"},{"key":"e_1_3_2_1_120_1","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-017-0152-y"},{"key":"e_1_3_2_1_121_1","doi-asserted-by":"publisher","DOI":"10.1145\/146628.139709"},{"key":"e_1_3_2_1_122_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00057"},{"key":"e_1_3_2_1_123_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346187"},{"key":"e_1_3_2_1_124_1","doi-asserted-by":"publisher","DOI":"10.1145\/379240.379246"},{"key":"e_1_3_2_1_125_1","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339676"}],"event":{"name":"ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems","location":"Lausanne Switzerland","acronym":"ASPLOS '22","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages","SIGOPS ACM Special Interest Group on Operating Systems","SIGARCH ACM Special Interest Group on Computer Architecture","SIGBED ACM Special Interest Group on Embedded Systems"]},"container-title":["Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3503222.3507745","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3503222.3507745","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T20:11:40Z","timestamp":1750191100000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3503222.3507745"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,2,22]]},"references-count":123,"alternative-id":["10.1145\/3503222.3507745","10.1145\/3503222"],"URL":"https:\/\/doi.org\/10.1145\/3503222.3507745","relation":{},"subject":[],"published":{"date-parts":[[2022,2,22]]},"assertion":[{"value":"2022-02-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}