{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:53:48Z","timestamp":1774367628165,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,4,13]],"date-time":"2022-04-13T00:00:00Z","timestamp":1649808000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"NSF","award":["CCF-1937396, CMMI-2038625, CCF-1854737, CCF-2106725"],"award-info":[{"award-number":["CCF-1937396, CMMI-2038625, CCF-1854737, CCF-2106725"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,4,13]]},"DOI":"10.1145\/3505170.3506723","type":"proceedings-article","created":{"date-parts":[[2022,4,14]],"date-time":"2022-04-14T00:07:38Z","timestamp":1649894858000},"page":"203-210","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Global Placement Exploiting Soft 2D Regularity"],"prefix":"10.1145","author":[{"given":"Donghao","family":"Fang","sequence":"first","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Boyang","family":"Zhang","sequence":"additional","affiliation":[{"name":"Rutgers University, New Brunswick, NJ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hailiang","family":"Hu","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, TX, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wuxi","family":"Li","sequence":"additional","affiliation":[{"name":"Xilinx Inc, San Jose, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bo","family":"Yuan","sequence":"additional","affiliation":[{"name":"Rutgers University, New Brunswick, NJ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[{"name":"Texas A&M University, College Station, NJ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,4,13]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"IEEE Vehicular Technology Conference. 2247--2251","author":"Takahiro","unstructured":"Takahiro Asai et al. 2000. A systolic array RLS processor . In IEEE Vehicular Technology Conference. 2247--2251 . Takahiro Asai et al. 2000. A systolic array RLS processor. In IEEE Vehicular Technology Conference. 2247--2251."},{"key":"e_1_3_2_1_2_1","volume-title":"ACM\/IEEE Design Automation Conference. 306--311","author":"H","unstructured":"H Cai et al. 1990. A data path layout assembler for high performance DSP circuits . In ACM\/IEEE Design Automation Conference. 306--311 . H Cai et al. 1990. A data path layout assembler for high performance DSP circuits. In ACM\/IEEE Design Automation Conference. 306--311."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/29.7554"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2859220"},{"key":"e_1_3_2_1_7_1","volume-title":"ACM\/IEEE Design Automation Conference. 762--767","author":"Sheng","unstructured":"Sheng Chou et al. 2012. Structure-aware placement for datapath-intensive circuit designs . In ACM\/IEEE Design Automation Conference. 762--767 . Sheng Chou et al. 2012. Structure-aware placement for datapath-intensive circuit designs. In ACM\/IEEE Design Automation Conference. 762--767."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907068"},{"key":"e_1_3_2_1_9_1","volume-title":"ACM\/IEEE Asia and South Pacific Design Automation Conference. 833--840","author":"Zhuolun","unstructured":"Zhuolun He et al. 2021. Physical synthesis for advanced neural network processors . In ACM\/IEEE Asia and South Pacific Design Automation Conference. 833--840 . Zhuolun He et al. 2021. Physical synthesis for advanced neural network processors. In ACM\/IEEE Asia and South Pacific Design Automation Conference. 833--840."},{"key":"e_1_3_2_1_10_1","first-page":"1","article-title":"New systolic array architecture for finite field division","volume":"15","author":"Atef Ibrahim","year":"2018","unstructured":"Atef Ibrahim et al. 2018 . New systolic array architecture for finite field division . IEICE Electronics Express 15 , 11 (2018), 1 -- 11 . Atef Ibrahim et al. 2018. New systolic array architecture for finite field division. IEICE Electronics Express 15, 11 (2018), 1--11.","journal-title":"IEICE Electronics Express"},{"key":"e_1_3_2_1_11_1","volume-title":"ACM International Symposium on Computer Architecture. 1--12","author":"Norman","unstructured":"Norman P. Jouppi et al. 2017. In-datacenter performance analysis of a tensor processing unit . In ACM International Symposium on Computer Architecture. 1--12 . Norman P. Jouppi et al. 2017. In-datacenter performance analysis of a tensor processing unit. In ACM International Symposium on Computer Architecture. 1--12."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2170567"},{"key":"e_1_3_2_1_13_1","volume-title":"IEEE International Conference on Field-Programmable Technology. 76--84","author":"Hongxin","unstructured":"Hongxin Kong et al. 2020. How Much Does Regularity Help FPGA Placement? . In IEEE International Conference on Field-Programmable Technology. 76--84 . Hongxin Kong et al. 2020. How Much Does Regularity Help FPGA Placement?. In IEEE International Conference on Field-Programmable Technology. 76--84."},{"key":"e_1_3_2_1_14_1","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design. 357--362","author":"Tao","unstructured":"Tao Lin et al. 2013. POLAR: Placement based on novel rough legalization and refinement . In IEEE\/ACM International Conference on Computer-Aided Design. 357--362 . Tao Lin et al. 2013. POLAR: Placement based on novel rough legalization and refinement. In IEEE\/ACM International Conference on Computer-Aided Design. 357--362."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2391263"},{"key":"e_1_3_2_1_16_1","volume-title":"IFIP Workshop on Logic and Architecture Synthesis. 110--117","author":"Raymond","unstructured":"Raymond XT Nijssen et al. 1996. Two-dimensional datapath regularity extraction . In IFIP Workshop on Logic and Architecture Synthesis. 110--117 . Raymond XT Nijssen et al. 1996. Two-dimensional datapath regularity extraction. In IFIP Workshop on Logic and Architecture Synthesis. 110--117."},{"key":"e_1_3_2_1_17_1","volume-title":"IEEE International Conference on Bioinformatics and Biomedicine. 758--762","author":"Johan","unstructured":"Johan Peltenburg et al. 2016. Maximizing systolic array efficiency to accelerate the PairHMM forward algorithm . In IEEE International Conference on Bioinformatics and Biomedicine. 758--762 . Johan Peltenburg et al. 2016. Maximizing systolic array efficiency to accelerate the PairHMM forward algorithm. In IEEE International Conference on Bioinformatics and Biomedicine. 758--762."},{"key":"e_1_3_2_1_18_1","volume-title":"Future Parallel Computers","author":"Quinton Patrice","unstructured":"Patrice Quinton . 1987. An introduction to systolic architectures . In Future Parallel Computers . Springer Berlin Heidelberg , 387--400. Patrice Quinton. 1987. An introduction to systolic architectures. In Future Parallel Computers. Springer Berlin Heidelberg, 387--400."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.5120\/3084-4222"},{"key":"e_1_3_2_1_20_1","volume-title":"ACM\/IEEE Design Automation Conference. 756--761","author":"Samuel","unstructured":"Samuel Ward et al. 2012. PADE: A High-Performance Mixed-Size Placer with Automatic Datapath Extraction and Evaluation through High-Dimensional Data Learning . In ACM\/IEEE Design Automation Conference. 756--761 . https:\/\/doi.org\/ 10.1145\/2228360.2228497 10.1145\/2228360.2228497 Samuel Ward et al. 2012. PADE: A High-Performance Mixed-Size Placer with Automatic Datapath Extraction and Evaluation through High-Dimensional Data Learning. In ACM\/IEEE Design Automation Conference. 756--761. https:\/\/doi.org\/ 10.1145\/2228360.2228497"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2233862"},{"key":"e_1_3_2_1_22_1","volume-title":"ACM\/IEEE Design Automation Conference. 1--6.","author":"Xuechao","unstructured":"Xuechao Wei et al. 2017. Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs . In ACM\/IEEE Design Automation Conference. 1--6. Xuechao Wei et al. 2017. Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs. In ACM\/IEEE Design Automation Conference. 1--6."},{"key":"e_1_3_2_1_23_1","volume-title":"IEEE International Conference on ASIC. 97--100","author":"Changqi","unstructured":"Changqi Yang et al. 2003. Standard-cell based data-path placement utilizing regularity . In IEEE International Conference on ASIC. 97--100 . Changqi Yang et al. 2003. Standard-cell based data-path placement utilizing regularity. In IEEE International Conference on ASIC. 97--100."},{"key":"e_1_3_2_1_24_1","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design. 264--270","author":"Tao T","unstructured":"T Tao Ye et al. 2000. Data path placement with regularity . In IEEE\/ACM International Conference on Computer-Aided Design. 264--270 . T Tao Ye et al. 2000. Data path placement with regularity. In IEEE\/ACM International Conference on Computer-Aided Design. 264--270."},{"key":"e_1_3_2_1_25_1","volume-title":"IEEE International Symposium on Circuits and Systems. 1--4.","author":"Jiaxi","unstructured":"Jiaxi Zhang et al. 2019. Frequency improvement of systolic array-based CNNs on FPGAs . In IEEE International Symposium on Circuits and Systems. 1--4. Jiaxi Zhang et al. 2019. Frequency improvement of systolic array-based CNNs on FPGAs. In IEEE International Symposium on Circuits and Systems. 1--4."}],"event":{"name":"ISPD '22: International Symposium on Physical Design","location":"Virtual Event Canada","acronym":"ISPD '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation","SIGCHI ACM Special Interest Group on Computer-Human Interaction"]},"container-title":["Proceedings of the 2022 International Symposium on Physical Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3505170.3506723","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3505170.3506723","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3505170.3506723","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T17:45:06Z","timestamp":1750268706000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3505170.3506723"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,13]]},"references-count":25,"alternative-id":["10.1145\/3505170.3506723","10.1145\/3505170"],"URL":"https:\/\/doi.org\/10.1145\/3505170.3506723","relation":{},"subject":[],"published":{"date-parts":[[2022,4,13]]},"assertion":[{"value":"2022-04-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}