{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:35:01Z","timestamp":1773246901779,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":41,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,10,30]],"date-time":"2022-10-30T00:00:00Z","timestamp":1667088000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Hong Kong Innovation and Technology Fund Project","award":["No. ITS\/170\/20"],"award-info":[{"award-number":["No. ITS\/170\/20"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,10,30]]},"DOI":"10.1145\/3508352.3549361","type":"proceedings-article","created":{"date-parts":[[2022,12,22]],"date-time":"2022-12-22T12:10:54Z","timestamp":1671711054000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration"],"prefix":"10.1145","author":[{"given":"Xinyi","family":"Zhou","sequence":"first","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junjie","family":"Ye","sequence":"additional","affiliation":[{"name":"Huawei Noah's Ark Lab, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chak-Wa","family":"Pui","sequence":"additional","affiliation":[{"name":"Huawei Noah's Ark Lab, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kun","family":"Shao","sequence":"additional","affiliation":[{"name":"Huawei Noah's Ark Lab, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guangliang","family":"Zhang","sequence":"additional","affiliation":[{"name":"HiSilicon, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bin","family":"Wang","sequence":"additional","affiliation":[{"name":"Huawei Noah's Ark Lab, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianye","family":"Hao","sequence":"additional","affiliation":[{"name":"Huawei Noah's Ark Lab, Beijing, China and Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guangyong","family":"Chen","sequence":"additional","affiliation":[{"name":"Zhejiang Lab, Hangzhou, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pheng Ann","family":"Heng","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong, Hong Kong, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,12,22]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.5120\/ijca2021921053"},{"key":"e_1_3_2_1_2_1","first-page":"216","volume-title":"Congestion aware layout driven logic synthesis,\" in IEEE\/ACM International Conference on Computer Aided Design","author":"Kutzschebauch T.","year":"2001","unstructured":"T. Kutzschebauch and L. Stok, \"Congestion aware layout driven logic synthesis,\" in IEEE\/ACM International Conference on Computer Aided Design, pp. 216--223, IEEE, 2001."},{"key":"e_1_3_2_1_3_1","first-page":"61","volume-title":"Aging-aware logic synthesis,\" in 2013 IEEE\/ACM International Conference on Computer-Aided Design","author":"Ebrahimi M.","year":"2013","unstructured":"M. Ebrahimi, F. Oboril, S. Kiamehr, and M. B. Tahoori, \"Aging-aware logic synthesis,\" in 2013 IEEE\/ACM International Conference on Computer-Aided Design, pp. 61--68, IEEE, 2013."},{"key":"e_1_3_2_1_4_1","first-page":"148","volume-title":"Power-aware FPGA logic synthesis using binary decision diagrams,\" in Proceedings of the 15th International Symposium on Field Programmable Gate Arrays","author":"Tinmaung K. O.","year":"2007","unstructured":"K. O. Tinmaung, D. Howland, and R. Tessier, \"Power-aware FPGA logic synthesis using binary decision diagrams,\" in Proceedings of the 15th International Symposium on Field Programmable Gate Arrays, pp. 148--155, 2007."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.298040"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.248073"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2015735"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.752924"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2305847"},{"key":"e_1_3_2_1_10_1","first-page":"337","volume-title":"Rapid gate sizing with fewer iterations of lagrangian relaxation,\" in 2017 IEEE\/ACM International Conference on Computer-Aided Design","author":"Sharma A.","year":"2017","unstructured":"A. Sharma, D. Chinnery, S. Dhamdhere, and C. Chu, \"Rapid gate sizing with fewer iterations of lagrangian relaxation,\" in 2017 IEEE\/ACM International Conference on Computer-Aided Design, pp. 337--343, IEEE, 2017."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2915324"},{"key":"e_1_3_2_1_12_1","first-page":"1042","volume-title":"Automation & Test in Europe Conference & Exhibition","author":"Wu G.","year":"2016","unstructured":"G. Wu and C. Chu, \"Simultaneous slack matching, gate sizing and repeater insertion for asynchronous circuits,\" in 2016 Design, Automation & Test in Europe Conference & Exhibition, pp. 1042--1047, IEEE, 2016."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415662"},{"key":"e_1_3_2_1_14_1","first-page":"1815","volume-title":"Automation & Test in Europe Conference & Exhibition","author":"Qu T.","year":"2021","unstructured":"T. Qu, Y. Lin, Z. Lu, Y. Su, and Y. Wei, \"Asynchronous reinforcement learning framework for net order exploration in detailed routing,\" in 2021 Design, Automation & Test in Europe Conference & Exhibition, pp. 1815--1820, IEEE, 2021."},{"key":"e_1_3_2_1_15_1","first-page":"929","volume-title":"Clock-aware ultrascale fpga placement with machine learning routability prediction,\" in 2017 IEEE\/ACM International Conference on Computer-Aided Design","author":"Pui C.-W.","year":"2017","unstructured":"C.-W. Pui, G. Chen, Y. Ma, E. F. Young, and B. Yu, \"Clock-aware ultrascale fpga placement with machine learning routability prediction,\" in 2017 IEEE\/ACM International Conference on Computer-Aided Design, pp. 929--936, IEEE, 2017."},{"key":"e_1_3_2_1_16_1","first-page":"1","volume-title":"High performance graph convolutional networks with applications in testability analysis,\" in Proceedings of the 56th Annual Design Automation Conference","author":"Ma Y.","year":"2019","unstructured":"Y. Ma, H. Ren, B. Khailany, H. Sikka, L. Luo, K. Natarajan, and B. Yu, \"High performance graph convolutional networks with applications in testability analysis,\" in Proceedings of the 56th Annual Design Automation Conference 2019, pp. 1--6, 2019."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415704"},{"key":"e_1_3_2_1_18_1","first-page":"733","volume-title":"RL-Sizer: VLSI gate sizing for timing optimization using deep reinforcement learning,\" in 58th ACM\/IEEE Design Automation Conference","author":"Lu Y.-C.","year":"2021","unstructured":"Y.-C. Lu, S. Nath, V. Khandelwal, and S. K. Lim, \"RL-Sizer: VLSI gate sizing for timing optimization using deep reinforcement learning,\" in 58th ACM\/IEEE Design Automation Conference, pp. 733--738, IEEE, 2021."},{"key":"e_1_3_2_1_19_1","first-page":"395","volume-title":"Gate sizing using lagrangian relaxation combined with a fast gradient-based pre-processing step,\" in Proceedings of the 2002 IEEE\/ACM international conference on Computer-aided design","author":"Tennakoon H.","year":"2002","unstructured":"H. Tennakoon and C. Sechen, \"Gate sizing using lagrangian relaxation combined with a fast gradient-based pre-processing step,\" in Proceedings of the 2002 IEEE\/ACM international conference on Computer-aided design, pp. 395--402, 2002."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3054912"},{"key":"e_1_3_2_1_21_1","first-page":"168","volume-title":"An improved benchmark suite for the ISPD-2013 discrete cell sizing contest,\" in Proc of ACM International Symposium on Physical Design","author":"Ozdal M. M.","year":"2013","unstructured":"M. M. Ozdal, C. Amin, A. Ayupov, S. Burns, G. Wilke, and C. Zhuo, \"An improved benchmark suite for the ISPD-2013 discrete cell sizing contest,\" in Proc of ACM International Symposium on Physical Design, pp. 168--170, 2013."},{"key":"e_1_3_2_1_22_1","volume-title":"Spectral networks and locally connected networks on graphs,\" in ICLR","author":"Bruna J.","year":"2014","unstructured":"J. Bruna, W. Zaremba, A. Szlam, and Y. Lecun, \"Spectral networks and locally connected networks on graphs,\" in ICLR, 2014."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2939672.2939754"},{"key":"e_1_3_2_1_24_1","volume-title":"I. Titov, and M. Welling, \"Modeling relational data with graph convolutional networks,\" in European Semantic Web Conference","author":"Schlichtkrull M.","year":"2018","unstructured":"M. Schlichtkrull, T. N. Kipf, P. Bloem, R. Van Den Berg, I. Titov, and M. Welling, \"Modeling relational data with graph convolutional networks,\" in European Semantic Web Conference, 2018."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/3308558.3313562"},{"key":"e_1_3_2_1_26_1","volume-title":"Reinforcement learning: An introduction","author":"Sutton R. S.","year":"2018","unstructured":"R. S. Sutton and A. G. Barto, Reinforcement learning: An introduction. MIT press, 2018."},{"key":"e_1_3_2_1_27_1","volume-title":"Human-level control through deep reinforcement learning,\" nature","author":"Mnih V.","unstructured":"V. Mnih, K. Kavukcuoglu, D. Silver, A. A. Rusu, J. Veness, M. G. Bellemare, A. Graves, M. Riedmiller, A. K. Fidjeland, G. Ostrovski, et al., \"Human-level control through deep reinforcement learning,\" nature, vol. 518, no. 7540, pp. 529--533, 2015."},{"key":"e_1_3_2_1_28_1","volume-title":"J. Schrittwieser, I. Antonoglou, V. Panneershelvam, M. Lanctot, et al., \"Mastering the game of go with deep neural networks and tree search,\" nature","author":"Silver D.","unstructured":"D. Silver, A. Huang, C. J. Maddison, A. Guez, L. Sifre, G. Van Den Driessche, J. Schrittwieser, I. Antonoglou, V. Panneershelvam, M. Lanctot, et al., \"Mastering the game of go with deep neural networks and tree search,\" nature, vol. 529, no. 7587, pp. 484--489, 2016."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.robot.2008.10.024"},{"key":"e_1_3_2_1_30_1","volume-title":"Active imitation learning via reduction to i.i.d. active learning,\" in 2012 AAAI Fall Symposium Series","author":"Judah K.","year":"2012","unstructured":"K. Judah, A. P. Fern, and T. G. Dietterich, \"Active imitation learning via reduction to i.i.d. active learning,\" in 2012 AAAI Fall Symposium Series, 2012."},{"key":"e_1_3_2_1_31_1","first-page":"1433","article-title":"Maximum entropy inverse reinforcement learning","volume":"8","author":"Ziebart B. D.","year":"2008","unstructured":"B. D. Ziebart, A. L. Maas, J. A. Bagnell, A. K. Dey, et al., \"Maximum entropy inverse reinforcement learning.,\" in AAAI, vol. 8, pp. 1433--1438, 2008.","journal-title":"AAAI"},{"key":"e_1_3_2_1_32_1","volume-title":"Towards out-of-distribution generalization: A survey,\" arXiv preprint arXiv:2108.13624","author":"Shen Z.","year":"2021","unstructured":"Z. Shen, J. Liu, Y. He, X. Zhang, R. Xu, H. Yu, and P. Cui, \"Towards out-of-distribution generalization: A survey,\" arXiv preprint arXiv:2108.13624, 2021."},{"key":"e_1_3_2_1_33_1","first-page":"5372","article-title":"Deep stable learning for out-of-distribution generalization","author":"Zhang X.","year":"2021","unstructured":"X. Zhang, P. Cui, R. Xu, L. Zhou, Y. He, and Z. Shen, \"Deep stable learning for out-of-distribution generalization,\" in Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition, pp. 5372--5382, 2021.","journal-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition"},{"key":"e_1_3_2_1_34_1","volume-title":"Relational inductive biases, deep learning, and graph networks,\" arXiv preprint arXiv:1806.01261","author":"Battaglia P. W.","year":"2018","unstructured":"P. W. Battaglia, J. B. Hamrick, V. Bapst, A. Sanchez-Gonzalez, V. Zambaldi, M. Malinowski, A. Tacchetti, D. Raposo, A. Santoro, R. Faulkner, et al., \"Relational inductive biases, deep learning, and graph networks,\" arXiv preprint arXiv:1806.01261, 2018."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1093\/bib\/bbab371"},{"key":"e_1_3_2_1_36_1","volume-title":"Tackling over-smoothing for general graph convolutional networks,\" arXiv preprint arXiv:2008.09864","author":"Huang W.","year":"2020","unstructured":"W. Huang, Y. Rong, T. Xu, F. Sun, and J. Huang, \"Tackling over-smoothing for general graph convolutional networks,\" arXiv preprint arXiv:2008.09864, 2020."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.trb.2013.10.012"},{"key":"e_1_3_2_1_38_1","first-page":"225","volume-title":"Lagrangian relaxation applied to sparse global network alignment,\" in IAPR International Conference on Pattern Recognition in Bioinformatics","author":"El-Kebir M.","year":"2011","unstructured":"M. El-Kebir, J. Heringa, and G. W. Klau, \"Lagrangian relaxation applied to sparse global network alignment,\" in IAPR International Conference on Pattern Recognition in Bioinformatics, pp. 225--236, Springer, 2011."},{"key":"e_1_3_2_1_39_1","first-page":"1846","article-title":"Multi-target tracking by lagrangian relaxation to min-cost network flow","author":"Butt A. A.","year":"2013","unstructured":"A. A. Butt and R. T. Collins, \"Multi-target tracking by lagrangian relaxation to min-cost network flow,\" in Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, pp. 1846--1853, 2013.","journal-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.trc.2010.03.007"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10479-011-0915-2"}],"event":{"name":"ICCAD '22: IEEE\/ACM International Conference on Computer-Aided Design","location":"San Diego California","acronym":"ICCAD '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-EDS Electronic Devices Society","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3549361","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3508352.3549361","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:30:23Z","timestamp":1750188623000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3549361"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,30]]},"references-count":41,"alternative-id":["10.1145\/3508352.3549361","10.1145\/3508352"],"URL":"https:\/\/doi.org\/10.1145\/3508352.3549361","relation":{},"subject":[],"published":{"date-parts":[[2022,10,30]]},"assertion":[{"value":"2022-12-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}