{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,25]],"date-time":"2026-07-25T16:52:09Z","timestamp":1784998329400,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":26,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,10,30]],"date-time":"2022-10-30T00:00:00Z","timestamp":1667088000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,10,30]]},"DOI":"10.1145\/3508352.3549367","type":"proceedings-article","created":{"date-parts":[[2022,12,22]],"date-time":"2022-12-22T12:10:54Z","timestamp":1671711054000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["Spatz"],"prefix":"10.1145","author":[{"given":"Matheus","family":"Cavalcante","sequence":"first","affiliation":[{"name":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Domenic","family":"W\u00fcthrich","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matteo","family":"Perotti","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Samuel","family":"Riedel","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"ETH Z\u00fcrich, Z\u00fcrich, Switzerland and Universit\u00e0 di Bologna, Bologna, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,12,22]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Arrow: A RISC-V Vector Accelerator for Machine Learning Inference. arXiv:2107.07169","author":"Al Assir I.","year":"2021","unstructured":"I. Al Assir, M. El Iskandarani, H. Al Sandid, and M. Saghir. 2021. Arrow: A RISC-V Vector Accelerator for Machine Learning Inference. arXiv:2107.07169"},{"key":"e_1_3_2_1_2_1","volume-title":"Introduction to Armv8.1-M architecture","author":"Arm Corp. 2019.","unstructured":"Arm Corp. 2019. Introduction to Armv8.1-M architecture. Arm Corp., Cambridge, UK. Revision r1p1."},{"key":"e_1_3_2_1_3_1","volume-title":"Arm Cortex-M55 Processor Datasheet","author":"Arm Corp. 2020.","unstructured":"Arm Corp. 2020. Arm Cortex-M55 Processor Datasheet. Arm Corp., Cambridge, UK. https:\/\/developer.arm.com\/documentation\/102833\/0100\/?lang=en"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359579"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","unstructured":"M. Cavalcante S. Riedel A. Pullini and L. Benini. 2021. MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. In 2021 Design Automation & Test in Europe Conference & Exhibition (DATE). IEEE Grenoble France 701--706. 10.23919\/DATE51398.2021.9474087","DOI":"10.23919\/DATE51398.2021.9474087"},{"key":"e_1_3_2_1_6_1","first-page":"530","article-title":"Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI","volume":"28","author":"Cavalcante M.","year":"2020","unstructured":"M. Cavalcante, F. Schuiki, F. Zaruba, and L. Benini. 2020. Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE TVLSI 28, 2 (2020), 530--543.","journal-title":"IEEE TVLSI"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_2_1_8_1","unstructured":"J. Domke E. Vatai B. Gerofi Y. Kodama M. Wahib A. Podobas S. Mittal M. Peric\u00e0s L. Zhang P. Chen A. Drozd and S. Matsuoka. 2022. At the Locus of Performance: A Case Study in Enhancing CPUs with Copious 3D-Stacked Cache. arXiv:2204.02235"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","unstructured":"M. Johns and T. J. Kazmierski. 2020. A Minimal RISC-V Vector Processor for Embedded Systems. In 2020 Forum for Specification and Design Languages (FDL). IEEE Kiel Germany 1--4. 10.1109\/FDL50818.2020.9232940","DOI":"10.1109\/FDL50818.2020.9232940"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261385"},{"key":"e_1_3_2_1_11_1","volume-title":"Vitruvius: And Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing. In RISC-V Summit","author":"Minervini F.","year":"2021","unstructured":"F. Minervini and O. Palomar. 2021. Vitruvius: And Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing. In RISC-V Summit 2021. RISC-V International, San Francisco, CA, USA."},{"key":"e_1_3_2_1_12_1","first-page":"11","article-title":"Progress in Digital Integrated Electronics. International Electron Devices Meeting","volume":"21","author":"Moore G. E.","year":"1975","unstructured":"G. E. Moore. 1975. Progress in Digital Integrated Electronics. International Electron Devices Meeting, IEEE 21 (1975), 11--13.","journal-title":"IEEE"},{"key":"e_1_3_2_1_13_1","volume-title":"Nvidia H100 Tensor Core GPU Architecture (1.02 ed.)","author":"NVIDIA Corp. 2022.","unstructured":"NVIDIA Corp. 2022. Nvidia H100 Tensor Core GPU Architecture (1.02 ed.). NVIDIA Corp. https:\/\/resources.nvidia.com\/en-us-tensor-core"},{"key":"e_1_3_2_1_14_1","volume-title":"OpenHW Group eXtension Interface","author":"OpenHW Corp. 2022.","unstructured":"OpenHW Corp. 2022. OpenHW Group eXtension Interface. OpenHW Corp. https:\/\/docs.openhwgroup.org\/projects\/openhw-group-core-v-xif Revision a3bcdd76."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.4230\/LIPIcs.ECRTS.2021.1"},{"key":"e_1_3_2_1_16_1","unstructured":"PULP Platform. 2021. MemPool. https:\/\/github.com\/pulp-platform\/mempool\/."},{"key":"e_1_3_2_1_17_1","volume-title":"version 1.0. https:\/\/github.com\/riscv\/riscv-v-spec Accessed on","author":"RISC-V Corp. 2022. RISC-V \"V\" Vector Extension","year":"2022","unstructured":"RISC-V Corp. 2022. RISC-V \"V\" Vector Extension, version 1.0. https:\/\/github.com\/riscv\/riscv-v-spec Accessed on April 16, 2022."},{"key":"e_1_3_2_1_18_1","first-page":"211","volume-title":"Proceedings Notebook for COOL Chips 25","author":"Shintani S.","year":"2022","unstructured":"S. Shintani. 2022. RISC-V-based Parallel Processor IP with Vector Extension for Embedded Systems. In Proceedings Notebook for COOL Chips 25. IEEE, IEEE, Tokyo, Japan, pp. 211--257."},{"key":"e_1_3_2_1_19_1","volume-title":"SiFive Intelligence X280 (21G3 ed.)","author":"SiFive Corp. 2022.","unstructured":"SiFive Corp. 2022. SiFive Intelligence X280 (21G3 ed.). SiFive Corp., San Mateo, CA, USA. https:\/\/sifive.cdn.prismic.io\/sifive\/62e0df53-be02-4b50-b211-aa55b7042fc8_x280-datasheet-21G3.pdf"},{"key":"e_1_3_2_1_20_1","volume-title":"SiFive Performance P270 (21G3 ed.)","author":"SiFive Corp. 2022.","unstructured":"SiFive Corp. 2022. SiFive Performance P270 (21G3 ed.). SiFive Corp., San Mateo, CA, USA. https:\/\/sifive.cdn.prismic.io\/sifive\/859c28c0-8bd5-4fc4-9113-a25a2a89bf9c_P270+Data+Sheet.pdf"},{"key":"e_1_3_2_1_21_1","volume-title":"Top500 List -","year":"2021","unstructured":"Top500. 2021. Top500 List - November 2021. https:\/\/www.top500.org\/lists\/top500\/2021\/11\/"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.3211127"},{"key":"e_1_3_2_1_23_1","volume-title":"Fujitsu High Performance CPU for the Post-K Computer. In Hot Chips: A Symposium on High Performance Chips (HC30)","author":"Yoshida T.","year":"2018","unstructured":"T. Yoshida. 2018. Fujitsu High Performance CPU for the Post-K Computer. In Hot Chips: A Symposium on High Performance Chips (HC30). IEEE, Cupertino, CA, USA, 1--22."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926114"},{"key":"e_1_3_2_1_25_1","volume-title":"2020 IEEE Hot Chips 32 Symposium (HC32)","author":"Zaruba F.","unstructured":"F. Zaruba, F. Schuiki, and L. Benini. 2020. Manticore: a 4096-core RISC-V chiplet architecture for ultra-efficient floating-point computing. In 2020 IEEE Hot Chips 32 Symposium (HC32). IEEE Technical Committee on Microprocessors and Microcomputers, IEEE, Cupertino, US, 36--42."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3027900"}],"event":{"name":"ICCAD '22: IEEE\/ACM International Conference on Computer-Aided Design","location":"San Diego California","acronym":"ICCAD '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-EDS Electronic Devices Society","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3549367","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3508352.3549367","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:30:23Z","timestamp":1750188623000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3549367"}},"subtitle":["A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters"],"short-title":[],"issued":{"date-parts":[[2022,10,30]]},"references-count":26,"alternative-id":["10.1145\/3508352.3549367","10.1145\/3508352"],"URL":"https:\/\/doi.org\/10.1145\/3508352.3549367","relation":{},"subject":[],"published":{"date-parts":[[2022,10,30]]},"assertion":[{"value":"2022-12-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}