{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T09:11:58Z","timestamp":1773825118430,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":37,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,10,30]],"date-time":"2022-10-30T00:00:00Z","timestamp":1667088000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,10,30]]},"DOI":"10.1145\/3508352.3549464","type":"proceedings-article","created":{"date-parts":[[2022,12,22]],"date-time":"2022-12-22T12:10:54Z","timestamp":1671711054000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["GIA"],"prefix":"10.1145","author":[{"given":"Fuping","family":"Li","sequence":"first","affiliation":[{"name":"University of Chinese Academy of Sciences"}]},{"given":"Ying","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences and Zhejiang Laboratory"}]},{"given":"Yuanqing","family":"Cheng","sequence":"additional","affiliation":[{"name":"Beihang University"}]},{"given":"Yujie","family":"Wang","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences and Zhejiang Laboratory"}]},{"given":"Yinhe","family":"Han","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences and Zhejiang Laboratory"}]},{"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences and Peng Cheng Laboratory"}]},{"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"University of Chinese Academy of Sciences"}]}],"member":"320","published-online":{"date-parts":[[2022,12,22]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Architecture and CAD for deep-submicron FPGAs","author":"Betz Vaughn","unstructured":"Vaughn Betz, Jonathan Rose, and Alexander Marquardt. 2012. Architecture and CAD for deep-submicron FPGAs. Vol. 497."},{"key":"e_1_3_2_1_2_1","volume-title":"Automation Test in Europe Conference Exhibition. 338--343","author":"Owen Chen Chia-Hsin","year":"2013","unstructured":"Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, and Li-Shiuan Peh. 2013. SMART: A single-cycle reconfigurable NoC for SoC applications. In Design, Automation Test in Europe Conference Exhibition. 338--343."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2970019"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/278241.278309"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714998"},{"key":"e_1_3_2_1_6_1","volume-title":"Automation Test in Europe Conference Exhibition. 1441--1446","author":"Eris Furkan","year":"2018","unstructured":"Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Saiful Mojumder, and Tiansheng Zhang. 2018. Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon. In Design, Automation Test in Europe Conference Exhibition. 1441--1446."},{"key":"e_1_3_2_1_7_1","volume-title":"Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration. arXiv preprint arXiv:2203.12268","author":"Feng Yinxiao","year":"2022","unstructured":"Yinxiao Feng and Kaisheng Ma. 2022. Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration. arXiv preprint arXiv:2203.12268 (2022)."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HCS49909.2020.9220557"},{"key":"e_1_3_2_1_9_1","volume-title":"As chip design costs skyrocket, 3nm process node is in jeopardy. ExtremeTech https:\/\/www.extremetech.com\/computing\/272096-3nm-process-node (22","author":"Hruska J","year":"2018","unstructured":"J Hruska. 2018. As chip design costs skyrocket, 3nm process node is in jeopardy. ExtremeTech https:\/\/www.extremetech.com\/computing\/272096-3nm-process-node (22 June 2018) (2018)."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.844106"},{"key":"e_1_3_2_1_11_1","volume-title":"Annual IEEE\/ACM International Symposium on Microarchitecture. 458--470","author":"Jerger Natalie Enright","unstructured":"Natalie Enright Jerger, Ajaykumar Kannan, Zimo Li, and Gabriel H. Loh. 2014. NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?. In Annual IEEE\/ACM International Symposium on Microarchitecture. 458--470."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01755-1"},{"key":"e_1_3_2_1_13_1","volume-title":"IEEE International Symposium on Performance Analysis of Systems and Software. 86--96","author":"Jiang Nan","unstructured":"Nan Jiang, Daniel U. Becker, George Michelogiannakis, James Balfour, Brian Towles, D. E. Shaw, John Kim, and William J. Dally. 2013. A detailed and flexible cycle-accurate Network-on-Chip simulator. In IEEE International Symposium on Performance Analysis of Systems and Software. 86--96."},{"key":"e_1_3_2_1_14_1","unstructured":"Jukka Jyl\u00e4nki. 2010. A thousand ways to pack the bin-a practical approach to two-dimensional rectangle bin packing. http:\/\/clb.demon.fi\/files\/RectangleBinPack.pdf (2010)."},{"key":"e_1_3_2_1_15_1","volume-title":"Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 546--558","author":"Kannan Ajaykumar","unstructured":"Ajaykumar Kannan, Natalie Enright Jerger, and Gabriel H. Loh. 2015. Enabling interposer-based disintegration of multi-core processors. In Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO). 546--558."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250693"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474011"},{"key":"e_1_3_2_1_18_1","volume-title":"IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis. 69--74","author":"Marculescu Radu","unstructured":"Radu Marculescu, Jingcao Hu, and Umit Y. Ogras. 2005. Key research problems in NoC design: a holistic perspective. In IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis. 69--74."},{"key":"e_1_3_2_1_19_1","article-title":"Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation","volume":"12","author":"Moon Peter","year":"2008","unstructured":"Peter Moon, Vinay Chikarmane, Kevin Fischer, Rohit Grover, Tarek A Ibrahim, Doug Ingerly, Kevin J Lee, Chris Litteken, Tony Mule, and Sarah Williams. 2008. Process and Electrical Results for the On-die Interconnect Stack for Intel's 45nm Process Generation. Intel Technology Journal 12, 2 (2008).","journal-title":"Intel Technology Journal"},{"key":"e_1_3_2_1_20_1","volume-title":"Designing Application-Specific Networks on Chips with Floorplan Information. In IEEE\/ACM International Conference on Computer Aided Design. 355--362","author":"Murali Srinivasan","year":"2006","unstructured":"Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, and Luigi Raffo. 2006. Designing Application-Specific Networks on Chips with Floorplan Information. In IEEE\/ACM International Conference on Computer Aided Design. 355--362."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00014"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.4071\/2380-4505-2019.1.000027"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586194"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2020.3033136"},{"key":"e_1_3_2_1_25_1","first-page":"52","article-title":"A 16nm 785GMACs\/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2x2 Dielet with 10um-Pitch Inter-Dielet I\/O for Runtime Multi-Program Reconfiguration","volume":"65","author":"Rathore Uneeb","year":"2022","unstructured":"Uneeb Rathore, Sumeet Singh Nagi, Subramanian Iyer, and Dejan Markovi\u0107. 2022. A 16nm 785GMACs\/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2x2 Dielet with 10um-Pitch Inter-Dielet I\/O for Runtime Multi-Program Reconfiguration. In IEEE International Solid- State Circuits Conference, Vol. 65. 52--54.","journal-title":"IEEE International Solid- State Circuits Conference"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNET.2003.813040"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980095"},{"key":"e_1_3_2_1_28_1","volume-title":"Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. In ACM\/IEEE International Workshop on System Level Interconnect Prediction. 1--8.","author":"Stow Dylan","year":"2019","unstructured":"Dylan Stow, Itir Akgun, and Yuan Xie. 2019. Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. In ACM\/IEEE International Workshop on System Level Interconnect Prediction. 1--8."},{"key":"e_1_3_2_1_29_1","volume-title":"IEEE\/ACM International Conference on Computer-Aided Design. 728--735","author":"Stow Dylan","unstructured":"Dylan Stow, Yuan Xie, Taniya Siddiqua, and Gabriel H. Loh. 2017. Cost-effective design of scalable high-performance systems using active and passive interposers. In IEEE\/ACM International Conference on Computer-Aided Design. 728--735."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_3_2_1_31_1","volume-title":"Shi Dong, and David Kaeli.","author":"Sun Yifan","year":"2019","unstructured":"Yifan Sun, Nicolas Bohm Agostini, Shi Dong, and David Kaeli. 2019. Summarizing CPU and GPU design trends with product data. arXiv preprint arXiv:1911.11313 (2019)."},{"key":"e_1_3_2_1_32_1","unstructured":"TechPowerUp. 2022. NVIDIA GeForce GT 1010. https:\/\/www.techpowerup.com\/gpu-specs\/geforce-gt-1010.c3762#:~:text=The%20GeForce%20GT%201010%20was run%20on%20GeForce%20GT%201010."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"crossref","unstructured":"P Vivet et al. 2020. A 220GOPS 96-core processor with 6 chiplets 3D-stacked on an active interposer offering 0.6 ns\/mm latency 3TBit\/s\/mm2 inter-chiplet interconnects and 156mW\/mm2@ 82% Peak-Efficiency DC-DC Converters. In Proc. IEEE Int. Conf. Solid-State Circuits.","DOI":"10.1109\/ISSCC19947.2020.9062927"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837313"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3085578"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2017.123"},{"key":"e_1_3_2_1_37_1","volume-title":"Validation, acceleration and extension","author":"Zhang Runjie","year":"2015","unstructured":"Runjie Zhang, Mircea R Stan, and Kevin Skadron. 2015. Hotspot 6.0: Validation, acceleration and extension. University of Virginia, Tech. Rep (2015)."}],"event":{"name":"ICCAD '22: IEEE\/ACM International Conference on Computer-Aided Design","location":"San Diego California","acronym":"ICCAD '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-EDS Electronic Devices Society","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3549464","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3508352.3549464","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:57Z","timestamp":1750186977000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3549464"}},"subtitle":["A Reusable General Interposer Architecture for Agile Chiplet Integration"],"short-title":[],"issued":{"date-parts":[[2022,10,30]]},"references-count":37,"alternative-id":["10.1145\/3508352.3549464","10.1145\/3508352"],"URL":"https:\/\/doi.org\/10.1145\/3508352.3549464","relation":{},"subject":[],"published":{"date-parts":[[2022,10,30]]},"assertion":[{"value":"2022-12-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}