{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,12]],"date-time":"2026-07-12T03:36:13Z","timestamp":1783827373787,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":40,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,10,30]],"date-time":"2022-10-30T00:00:00Z","timestamp":1667088000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,10,30]]},"DOI":"10.1145\/3508352.3561093","type":"proceedings-article","created":{"date-parts":[[2022,12,22]],"date-time":"2022-12-22T12:10:54Z","timestamp":1671711054000},"page":"1-8","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":15,"title":["Why are Graph Neural Networks Effective for EDA Problems?"],"prefix":"10.1145","author":[{"given":"Haoxing","family":"Ren","sequence":"first","affiliation":[{"name":"NVIDIA Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Siddhartha","family":"Nath","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yanqing","family":"Zhang","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hao","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mingjie","family":"Liu","sequence":"additional","affiliation":[{"name":"University of Texas at Austin"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,12,22]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"00596","article-title":"A comprehensive survey on graph neural networks","volume":"1901","author":"Wu Z.","year":"2019","unstructured":"Z. Wu et al., \"A comprehensive survey on graph neural networks,\" CoRR, vol. abs\/1901.00596, 2019. [Online]. Available: http:\/\/arxiv.org\/abs\/1901.00596","journal-title":"CoRR"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317838"},{"key":"e_1_3_2_1_3_1","volume-title":"GRANNITE: Graph Neural Network Inference for Transferable Power Estimation,\" in Proceedings of the 57th ACM\/EDAC\/IEEE Design Automation Conference","author":"Zhang Y.","year":"2020","unstructured":"Y. Zhang, H. Ren, and B. Khailany, \"GRANNITE: Graph Neural Network Inference for Transferable Power Estimation,\" in Proceedings of the 57th ACM\/EDAC\/IEEE Design Automation Conference, 2020."},{"key":"e_1_3_2_1_4_1","first-page":"1243","volume-title":"Universal symmetry constraint extraction for analog and mixed-signal circuits with graph neural networks,\" in ACM\/IEEE Design Automation Conference (DAC)","author":"Chen H.","year":"2021","unstructured":"H. Chen et al., \"Universal symmetry constraint extraction for analog and mixed-signal circuits with graph neural networks,\" in ACM\/IEEE Design Automation Conference (DAC), 2021, pp. 1243--1248."},{"key":"e_1_3_2_1_5_1","volume-title":"ACM","author":"Guo Z.","year":"2022","unstructured":"Z. Guo et al., \"A timing engine inspired graph neural network model for pre-routing slack prediction,\" in Proceedings of the 59th Annual Design Automation Conference 2022. ACM, 2022."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1038\/s42254-021-00314-5"},{"key":"e_1_3_2_1_7_1","first-page":"02907","article-title":"Semi-supervised classification with graph convolutional networks","volume":"1609","author":"Kipf T. N.","year":"2016","unstructured":"T. N. Kipf and M. Welling, \"Semi-supervised classification with graph convolutional networks,\" CoRR, vol. abs\/1609.02907, 2016.","journal-title":"CoRR"},{"key":"e_1_3_2_1_8_1","volume-title":"Inductive Representation Learning on Large Graphs","author":"Hamilton W. L.","year":"2017","unstructured":"W. L. Hamilton, R. Ying, and J. Leskovec, \"Inductive Representation Learning on Large Graphs,\" 2017. [Online]. Available: https:\/\/arxiv.org\/abs\/1706.02216"},{"key":"e_1_3_2_1_9_1","first-page":"10903","article-title":"Graph attention networks","volume":"1710","author":"Velickovic P.","year":"2017","unstructured":"P. Velickovic et al., \"Graph attention networks,\" ArXiv, vol. abs\/1710.10903, 2017.","journal-title":"ArXiv"},{"key":"e_1_3_2_1_10_1","first-page":"15091","article-title":"Inductive biases for deep learning of higher-level cognition","volume":"2011","author":"Goyal A.","year":"2020","unstructured":"A. Goyal and Y. Bengio, \"Inductive biases for deep learning of higher-level cognition,\" CoRR, vol. abs\/2011.15091, 2020. [Online]. Available: https:\/\/arxiv.org\/abs\/2011.15091","journal-title":"CoRR"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530601"},{"key":"e_1_3_2_1_12_1","first-page":"511","volume-title":"MWSCAS-2002","volume":"1","author":"Nourani M.","year":"2002","unstructured":"M. Nourani, S. Nazarian, and A. Afzali-Kusha, \"A Parallel Algorithm for Power Estimation at Gate Level,\" in The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002., vol. 1, 2002, pp. I--511."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217599"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996626"},{"key":"e_1_3_2_1_15_1","first-page":"1","volume-title":"Paragraph: Layout parasitics and device parameter prediction using graph neural networks,\" in 2020 57th ACM\/IEEE Design Automation Conference (DAC)","author":"Ren H.","year":"2020","unstructured":"H. Ren et al., \"Paragraph: Layout parasitics and device parameter prediction using graph neural networks,\" in 2020 57th ACM\/IEEE Design Automation Conference (DAC), 2020, pp. 1--6."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-93417-4_38"},{"key":"e_1_3_2_1_17_1","volume-title":"The Art of Analog Layout","author":"Hastings A.","year":"2001","unstructured":"A. Hastings and R. A. Hastings, The Art of Analog Layout, 1st ed. USA: Prentice Hall, 2001.","edition":"1"},{"key":"e_1_3_2_1_18_1","first-page":"561","volume-title":"Constraint generation for routing analog circuits,\" in ACM\/IEEE Design Automation Conference (DAC)","author":"Choudhury U.","year":"1990","unstructured":"U. Choudhury and A. Sangiovanni-Vincentelli, \"Constraint generation for routing analog circuits,\" in ACM\/IEEE Design Automation Conference (DAC), 1990, pp. 561--566."},{"key":"e_1_3_2_1_19_1","first-page":"408","article-title":"Generalized constraint generation for analog circuit design","author":"Charbon E.","year":"1993","unstructured":"E. Charbon, E. Malavasi, and A. Sangiovanni-Vincentelli, \"Generalized constraint generation for analog circuit design,\" in IEEE\/ACM International Conference on Computer-Aided Design, 1993, pp. 408--414.","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"e_1_3_2_1_20_1","first-page":"1","article-title":"MAGICAL 1.0: An open-source fully-automated ams layout synthesis framework verified with a 40-nm 1gs\/s \u0394σ adc","author":"Chen H.","year":"2021","unstructured":"H. Chen et al., \"MAGICAL 1.0: An open-source fully-automated ams layout synthesis framework verified with a 40-nm 1gs\/s \u0394σ adc,\" in IEEE Custom Integrated Circuits Conference (CICC), 2021, pp. 1--2.","journal-title":"IEEE Custom Integrated Circuits Conference (CICC)"},{"key":"e_1_3_2_1_21_1","first-page":"193","volume-title":"S3DET: Detecting system symmetry constraints for analog circuits with graph similarity,\" in IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC)","author":"Liu M.","year":"2020","unstructured":"M. Liu et al., \"S3DET: Detecting system symmetry constraints for analog circuits with graph similarity,\" in IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2020, pp. 193--198."},{"key":"e_1_3_2_1_22_1","first-page":"152","volume-title":"Layout symmetry annotation for analog circuits with graph neural networks,\" in IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC)","author":"Gao X.","year":"2021","unstructured":"X. Gao et al., \"Layout symmetry annotation for analog circuits with graph neural networks,\" in IEEE\/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2021, pp. 152--157."},{"key":"e_1_3_2_1_23_1","first-page":"1","article-title":"A general approach for identifying hierarchical symmetry constraints for analog circuit layout","author":"Kunal K.","year":"2020","unstructured":"K. Kunal et al., \"A general approach for identifying hierarchical symmetry constraints for analog circuit layout,\" in IEEE\/ACM International Conference on Computer-Aided Design, 2020, pp. 1--8.","journal-title":"IEEE\/ACM International Conference on Computer-Aided Design"},{"key":"e_1_3_2_1_24_1","first-page":"1","volume-title":"Gated graph sequence neural networks,\" in International Conference on Learning Representations (ICLR)","author":"Li Y.","year":"2016","unstructured":"Y. Li et al., \"Gated graph sequence neural networks,\" in International Conference on Learning Representations (ICLR), 2016, pp. 1--20."},{"key":"e_1_3_2_1_25_1","first-page":"706","volume-title":"Accurate estimation of global buffer delay within a floorplan,\" in IEEE\/ACM International Conference on Computer Aided Design","author":"Alpert C.","year":"2004","unstructured":"C. Alpert et al., \"Accurate estimation of global buffer delay within a floorplan,\" in IEEE\/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004., 2004, pp. 706--711."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996646"},{"key":"e_1_3_2_1_27_1","volume-title":"ACM","author":"Guo Z.","year":"2022","unstructured":"Z. Guo and Y. Lin, \"Differentiable-timing-driven global placement,\" in Proceedings of the 59th Annual Design Automation Conference 2022. ACM, 2022."},{"key":"e_1_3_2_1_28_1","first-page":"1","volume-title":"Machine learning-based pre-routing timing prediction with reduced pessimism,\" in 2019 56th ACM\/IEEE Design Automation Conference (DAC)","author":"Barboza E. C.","year":"2019","unstructured":"E. C. Barboza et al., \"Machine learning-based pre-routing timing prediction with reduced pessimism,\" in 2019 56th ACM\/IEEE Design Automation Conference (DAC), 2019, pp. 1--6."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431562"},{"key":"e_1_3_2_1_30_1","first-page":"10746","article-title":"Chip placement with deep reinforcement learning","volume":"2004","author":"Mirhoseini A.","year":"2020","unstructured":"A. Mirhoseini et al., \"Chip placement with deep reinforcement learning,\" CoRR, vol. abs\/2004.10746, 2020. [Online]. Available: https:\/\/arxiv.org\/abs\/2004.10746","journal-title":"CoRR"},{"key":"e_1_3_2_1_31_1","first-page":"1291","volume-title":"Invited- nvcell: Standard cell layout in advanced technology nodes with reinforcement learning,\" in 2021 58th ACM\/IEEE Design Automation Conference (DAC)","author":"Ren H.","year":"2021","unstructured":"H. Ren and M. Fojtik, \"Invited- nvcell: Standard cell layout in advanced technology nodes with reinforcement learning,\" in 2021 58th ACM\/IEEE Design Automation Conference (DAC), 2021, pp. 1291--1294."},{"key":"e_1_3_2_1_32_1","first-page":"01212","article-title":"Neural message passing for quantum chemistry","volume":"1704","author":"Gilmer J.","year":"2017","unstructured":"J. Gilmer et al., \"Neural message passing for quantum chemistry,\" CoRR, vol. abs\/1704.01212, 2017. [Online]. Available: http:\/\/arxiv.org\/abs\/1704.01212","journal-title":"CoRR"},{"key":"e_1_3_2_1_33_1","first-page":"06347","article-title":"Proximal policy optimization algorithms","volume":"1707","author":"Schulman J.","year":"2017","unstructured":"J. Schulman et al., \"Proximal policy optimization algorithms,\" CoRR, vol. abs\/1707.06347, 2017. [Online]. Available: http:\/\/arxiv.org\/abs\/1707.06347","journal-title":"CoRR"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586138"},{"key":"e_1_3_2_1_35_1","first-page":"00826","article-title":"How powerful are graph neural networks?","volume":"1810","author":"Xu K.","year":"2018","unstructured":"K. Xu et al., \"How powerful are graph neural networks?\" CoRR, vol. abs\/1810.00826, 2018. [Online]. Available: http:\/\/arxiv.org\/abs\/1810.00826","journal-title":"CoRR"},{"key":"e_1_3_2_1_36_1","volume-title":"Deep graph library: A graph-centric, highly-performant package for graph neural networks,\" arXiv preprint arXiv:1909.01315","author":"Wang M.","year":"2019","unstructured":"M. Wang et al., \"Deep graph library: A graph-centric, highly-performant package for graph neural networks,\" arXiv preprint arXiv:1909.01315, 2019."},{"key":"e_1_3_2_1_37_1","volume-title":"Fast graph representation learning with PyTorch Geometric,\" in ICLR Workshop on Representation Learning on Graphs and Manifolds","author":"Fey M.","year":"2019","unstructured":"M. Fey and J. E. Lenssen, \"Fast graph representation learning with PyTorch Geometric,\" in ICLR Workshop on Representation Learning on Graphs and Manifolds, 2019."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TKDE.2021.3090866","article-title":"Self-supervised learning: Generative or contrastive","author":"Liu X.","year":"2021","unstructured":"X. Liu et al., \"Self-supervised learning: Generative or contrastive,\" IEEE Transactions on Knowledge and Data Engineering, pp. 1--1, 2021.","journal-title":"IEEE Transactions on Knowledge and Data Engineering"},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TKDE.2022.3172903","article-title":"Graph self-supervised learning: A survey","author":"Liu Y.","year":"2022","unstructured":"Y. Liu et al., \"Graph self-supervised learning: A survey,\" IEEE Transactions on Knowledge and Data Engineering, pp. 1--1, 2022.","journal-title":"IEEE Transactions on Knowledge and Data Engineering"},{"key":"e_1_3_2_1_40_1","volume-title":"Functionality matters in netlist representation learning,\" in 2022 58th ACM\/IEEE Design Automation Conference (DAC)","author":"Wang Z.","year":"2022","unstructured":"Z. Wang et al., \"Functionality matters in netlist representation learning,\" in 2022 58th ACM\/IEEE Design Automation Conference (DAC), 2022."}],"event":{"name":"ICCAD '22: IEEE\/ACM International Conference on Computer-Aided Design","location":"San Diego California","acronym":"ICCAD '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-EDS Electronic Devices Society","IEEE CAS","IEEE CEDA"]},"container-title":["Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3561093","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3508352.3561093","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:49:36Z","timestamp":1750182576000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3561093"}},"subtitle":["(Invited Paper)"],"short-title":[],"issued":{"date-parts":[[2022,10,30]]},"references-count":40,"alternative-id":["10.1145\/3508352.3561093","10.1145\/3508352"],"URL":"https:\/\/doi.org\/10.1145\/3508352.3561093","relation":{},"subject":[],"published":{"date-parts":[[2022,10,30]]},"assertion":[{"value":"2022-12-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}