{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T10:04:42Z","timestamp":1764842682139,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":41,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,10,30]],"date-time":"2022-10-30T00:00:00Z","timestamp":1667088000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000183","name":"Army Research Office","doi-asserted-by":"publisher","award":["W911NF-19-1-0476"],"award-info":[{"award-number":["W911NF-19-1-0476"]}],"id":[{"id":"10.13039\/100000183","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,10,30]]},"DOI":"10.1145\/3508352.3561102","type":"proceedings-article","created":{"date-parts":[[2022,12,22]],"date-time":"2022-12-22T12:10:54Z","timestamp":1671711054000},"page":"1-9","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components"],"prefix":"10.1145","author":[{"given":"Maico Cassel dos","family":"Santos","sequence":"first","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianyu","family":"Jia","sequence":"additional","affiliation":[{"name":"Harvard University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin","family":"Cochet","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karthik","family":"Swaminathan","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph","family":"Zuckerman","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paolo","family":"Mantovani","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Davide","family":"Giri","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeff Jun","family":"Zhang","sequence":"additional","affiliation":[{"name":"Harvard University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Erik Jens","family":"Loscalzo","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriele","family":"Tombesi","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Tien","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nandhini","family":"Chandramoorthy","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John-David","family":"Wellman","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Brooks","sequence":"additional","affiliation":[{"name":"Harvard University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gu-Yeon","family":"Wei","sequence":"additional","affiliation":[{"name":"Harvard University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kenneth","family":"Shepard","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca P.","family":"Carloni","sequence":"additional","affiliation":[{"name":"Columbia University"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pradip","family":"Bose","sequence":"additional","affiliation":[{"name":"IBM Research"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,12,22]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"1","article-title":". IEEE Standard for Test Access Port and Boundary-Scan Architecture - Redline","volume":"1149","year":"2013","unstructured":"2013. IEEE Standard for Test Access Port and Boundary-Scan Architecture - Redline. IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001) - Redline (2013), 1--899.","journal-title":"IEEE Std"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_2_1","DOI":"10.1109\/IEEESTD.2019.8686430"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_3_1","DOI":"10.1109\/MM.2020.2996616"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_4_1","DOI":"10.1109\/N-SSC.2007.4785534"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_5_1","DOI":"10.1109\/JPROC.2015.2480849"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_6_1","DOI":"10.1145\/2897937.2905018"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_7_1","DOI":"10.1145\/3338698.3338893"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_8_1","DOI":"10.1109\/43.945302"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_9_1","DOI":"10.1109\/JPROC.2012.2190155"},{"unstructured":"Cobham Gaisler. [n.d.]. GRLIB IP Library. https:\/\/www.gaisler.com\/index.php\/downloads\/leongrlib.","key":"e_1_3_2_1_10_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_11_1","DOI":"10.1109\/HOTCHIPS.2013.7478302"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_12_1","DOI":"10.1145\/2744769.2744794"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_13_1","DOI":"10.1145\/3361682"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_14_1","DOI":"10.1109\/JSSC.1974.1050511"},{"unstructured":"Cobham Gaisler. [n.d.]. LEON3 Processor. www.gaisler.com\/index.php\/products\/processors\/leon3.","key":"e_1_3_2_1_15_1"},{"volume-title":"Proceedings of the Design, Automation and Test in Europe Conference (DATE).","author":"Giri Davide","unstructured":"Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, and Luca P. Carloni. 2020. ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning. Proceedings of the Design, Automation and Test in Europe Conference (DATE).","key":"e_1_3_2_1_16_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_17_1","DOI":"10.1109\/MM.2021.3073893"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_18_1","DOI":"10.1109\/MM.2018.2877288"},{"volume-title":"Proceedings of the Twelfth IEEE\/ACM International Symposium on Networks-on-Chip (NOCS).","author":"Giri Davide","unstructured":"Davide Giri, Paolo Mantovani, and Luca P. Carloni. 2018. NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators. Proceedings of the Twelfth IEEE\/ACM International Symposium on Networks-on-Chip (NOCS).","key":"e_1_3_2_1_19_1"},{"volume-title":"Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC).","author":"Giri Davide","unstructured":"Davide Giri, Paolo Mantovani, and Luca P. Carloni. 2019. Runtime Reconfigurable Memory Hierarchy in Embedded Scalable Platforms. Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC).","key":"e_1_3_2_1_20_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_21_1","DOI":"10.1109\/MC.2017.162"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_22_1","DOI":"10.1109\/ISSCC.2014.6757323"},{"unstructured":"Marko Isom\u00e4ki. 2004. Processor Debugging Through Ethernet. Master's thesis.","key":"e_1_3_2_1_23_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_24_1","DOI":"10.1109\/ESSCIRC55480.2022.9911456"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_25_1","DOI":"10.1109\/DAC.2018.8465897"},{"unstructured":"lowRISC. [n.d.]. IbexRISC-V Core. https:\/\/github.com\/lowRISC\/ibex.","key":"e_1_3_2_1_26_1"},{"key":"e_1_3_2_1_27_1","first-page":"1","article-title":"An FPGA-based Infrastructure for Fine-grained DVFS Analysis in High-performance Embedded Systems","volume":"157","author":"Mantovani Paolo","year":"2016","unstructured":"Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe Di Guglielmo, Ken Shepard, and Luca P. Carloni. 2016. An FPGA-based Infrastructure for Fine-grained DVFS Analysis in High-performance Embedded Systems. In Proceedings of the Design Automation Conference (DAC). 157:1--157:6.","journal-title":"Proceedings of the Design Automation Conference (DAC)."},{"volume-title":"2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD). 1--9.","author":"Mantovani Paolo","unstructured":"Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, and Luca P. Carloni. 2020. Agile SoC Development with Open ESP : Invited Paper. In 2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD). 1--9.","key":"e_1_3_2_1_28_1"},{"doi-asserted-by":"publisher","unstructured":"Azalia Mirhoseini Anna Goldie Mustafa Yazgan Joe Wenjie Jiang Ebrahim Songhori Shen Wang Young-Joon Lee Eric Johnson Omkar Pathak Azade Nazi Jiwoo Pak Andy Tong Kavya Srinivasa William Hang Emre Tuncer Quoc V. Le James Laudon Richard Ho Roger Carpenter and Jeff Dean. 2021. A graph placement methodology for fast chip design. Nature 594 7862 (2021) 207--212. 10.1038\/s41586-021-03544-w","key":"e_1_3_2_1_29_1","DOI":"10.1038\/s41586-021-03544-w"},{"unstructured":"NVIDIA. 2017. NVIDIA Deep Learning Accelerator (NVDLA). www.nvdla.org.","key":"e_1_3_2_1_30_1"},{"unstructured":"OpenLANE. [n.d.]. . https:\/\/github.com\/The-OpenROAD-Project\/OpenLane","key":"e_1_3_2_1_31_1"},{"unstructured":"RISC-V. [n.d.]. . Retrieved July 31 2022 from https:\/\/riscv.org\/","key":"e_1_3_2_1_32_1"},{"unstructured":"hls4ml. [n.d.]. https:\/\/fastmachinelearning.org\/hls4ml.","key":"e_1_3_2_1_33_1"},{"unstructured":"SkyWater. [n.d.]. . https:\/\/github.com\/google\/skywater-pdk","key":"e_1_3_2_1_34_1"},{"key":"e_1_3_2_1_35_1","volume-title":"Retrieved","author":"Sperling Ed","year":"2014","unstructured":"Ed Sperling. 2014. How much will that chip cost? Retrieved July 31, 2022 from http:\/\/semiengineering.com\/how-much-will-that-chip-cost\/"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_36_1","DOI":"10.1109\/ISQED48828.2020.9136999"},{"unstructured":"Rich Wawrzyniak. 2021. Analyzing RISC-V CPU market for SiP SoCs AI and Design Starts. https:\/\/semico.com\/content\/analyzing-risc-v-cpu-market-sip-socs-ai-and-design-starts\/","key":"e_1_3_2_1_37_1"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_38_1","DOI":"10.1109\/TCAD.2013.2276399"},{"doi-asserted-by":"publisher","key":"e_1_3_2_1_39_1","DOI":"10.1109\/TVLSI.2019.2926114"},{"volume-title":"Proceedings of the IEEE\/ACM Symposium on Microarchitecture (MICRO).","author":"Zuckerman Joseph","unstructured":"Joseph Zuckerman, Davide Giri, Jihye Kwon, Paolo Mantovani, and Luca P. Carloni. 2021. Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs. In Proceedings of the IEEE\/ACM Symposium on Microarchitecture (MICRO).","key":"e_1_3_2_1_40_1"},{"volume-title":"Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV).","author":"Zuckerman Joseph","unstructured":"Joseph Zuckerman, Paolo Mantovani, Davide Giri, and Luca P. Carloni. 2022. Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESP. Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV).","key":"e_1_3_2_1_41_1"}],"event":{"sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE-EDS Electronic Devices Society","IEEE CAS","IEEE CEDA"],"acronym":"ICCAD '22","name":"ICCAD '22: IEEE\/ACM International Conference on Computer-Aided Design","location":"San Diego California"},"container-title":["Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3561102","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3508352.3561102","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3508352.3561102","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:49:36Z","timestamp":1750182576000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3508352.3561102"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,30]]},"references-count":41,"alternative-id":["10.1145\/3508352.3561102","10.1145\/3508352"],"URL":"https:\/\/doi.org\/10.1145\/3508352.3561102","relation":{},"subject":[],"published":{"date-parts":[[2022,10,30]]},"assertion":[{"value":"2022-12-22","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}