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While Moore\u2019s law guided the semiconductor industry to cram more and more transistors and logic into the same volume, the limits of instruction-level parallelism (ILP) and the end of Dennard\u2019s scaling drove the industry towards multi-core chips. More recently, we have entered the era of domain-specific architectures (DSA) and chips for new workloads like artificial intelligence (AI) and machine learning (ML). These trends continue, arguably with other limits, along with challenges imposed by tighter integration, extreme form factors and increasingly diverse workloads, making systems more complex to architect, design, implement and optimize from an energy efficiency perspective. Energy efficiency has now become a first order design parameter and constraint across the entire spectrum of computing devices.<\/jats:p>\n          <jats:p>\n            Many research surveys have gone into different aspects of energy efficiency techniques implemented in hardware and microarchitecture across devices, servers, HPC\/cloud, data center systems along with improved software, algorithms, frameworks, and modeling energy\/thermals. Somewhat in parallel, the semiconductor industry has developed techniques and standards around specification, modeling\/simulation, benchmarking and verification of complex chips; these areas have not been addressed in detail by previous research surveys. This survey aims to bring these domains holistically together, present the latest in each of these areas, highlight potential gaps and challenges, and discuss opportunities for the next generation of energy efficient systems. The survey is composed of a systematic categorization of key aspects of building energy efficient systems - (1)\n            <jats:italic>specification<\/jats:italic>\n            - the ability to precisely specify the power intent, attributes or properties at different layers (2)\n            <jats:italic>modeling<\/jats:italic>\n            and\n            <jats:italic>simulation<\/jats:italic>\n            of the entire system or subsystem (hardware or software or both) so as to be able to experiment with possible options and perform what-if analysis, (3)\n            <jats:italic>techniques<\/jats:italic>\n            used for implementing energy efficiency at different levels of the stack, (4)\n            <jats:italic>verification<\/jats:italic>\n            techniques used to provide guarantees that the functionality of complex designs are preserved, and (5)\n            <jats:italic>energy efficiency benchmarks, standards and consortiums<\/jats:italic>\n            that aim to standardize different aspects of energy efficiency, including cross-layer optimizations.\n          <\/jats:p>","DOI":"10.1145\/3511094","type":"journal-article","created":{"date-parts":[[2022,2,10]],"date-time":"2022-02-10T18:07:05Z","timestamp":1644516425000},"page":"1-37","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":74,"title":["Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards"],"prefix":"10.1145","volume":"54","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3222-3738","authenticated-orcid":false,"given":"Rajeev","family":"Muralidhar","sequence":"first","affiliation":[{"name":"The University of Melbourne and Amazon Web Services, Australia"}]},{"given":"Renata","family":"Borovica-Gajic","sequence":"additional","affiliation":[{"name":"The University of Melbourne, Parkville, Victoria, Australia"}]},{"given":"Rajkumar","family":"Buyya","sequence":"additional","affiliation":[{"name":"The University of Melbourne, Parkville, Victoria, Australia"}]}],"member":"320","published-online":{"date-parts":[[2022,9,9]]},"reference":[{"key":"e_1_3_1_2_2","unstructured":"R 2011 AMD Claims \u2018Fastest Graphics Card in the World\u2019"},{"key":"e_1_3_1_3_2","unstructured":"01.org. 2020. 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