{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T15:03:10Z","timestamp":1773154990207,"version":"3.50.1"},"reference-count":34,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T00:00:00Z","timestamp":1654473600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2022,12,31]]},"abstract":"<jats:p>This work demonstrates a novel method of accelerating FPGA aging by configuring FPGAs to implement thousands of short circuits, resulting in high on-chip currents and temperatures. Patterns of ring oscillators are placed across the chip and are used to characterize the operating frequency of the FPGA fabric.<\/jats:p>\n          <jats:p>Over the course of several months of running the short circuits on two-thirds of the reconfigurable fabric, with daily characterization of the FPGA 6 performance, we demonstrate a decrease in FPGA frequency of 8.5%. We demonstrate that this aging is induced in a non-uniform manner. The maximum slowdown outside of the shorted regions is 2.1%, or about a fourth of the maximum slowdown that is experienced inside the shorted region. In addition, we demonstrate that the slowdown is linear after the first two weeks of the experiment and is unaffected by a recovery period.<\/jats:p>\n          <jats:p>Additional experiments involving short circuits are also performed to demonstrate the results of our initial experiments are repeatable. These experiments also use a more fine-grained characterization method that provides further insight into the non-uniformed nature of the aging caused by short circuits.<\/jats:p>","DOI":"10.1145\/3517042","type":"journal-article","created":{"date-parts":[[2022,2,11]],"date-time":"2022-02-11T18:09:47Z","timestamp":1644602987000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits"],"prefix":"10.1145","volume":"15","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1067-0054","authenticated-orcid":false,"given":"Hayden","family":"Cook","sequence":"first","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacob","family":"Arscott","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brent","family":"George","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tanner","family":"Gaskin","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9822-6926","authenticated-orcid":false,"given":"Jeffrey","family":"Goeders","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brad","family":"Hutchings","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,6,6]]},"reference":[{"key":"e_1_3_1_2_2"},{"key":"e_1_3_1_3_2"},{"key":"e_1_3_1_4_2"},{"key":"e_1_3_1_5_2"},{"key":"e_1_3_1_6_2"},{"key":"e_1_3_1_7_2","unstructured":"N. H. E. Weste and D. Harris. 2005. CMOS VLSI Design A Circuits and Systems Perspective MA Reading:Addison-Wesley. http:\/\/swarm.cs.pub.ro\/mbarbulescu\/SMPA\/CMOS-VLSI-design.pdf."},{"key":"e_1_3_1_8_2","unstructured":"JEDEC Solid State Technology Association and others. JEP122C. ([n. d.]). https:\/\/citeseerx.ist.psu.edu\/viewdoc\/download?doi=10.1.1.478.4344&rep=rep1&type=pdf."},{"key":"e_1_3_1_9_2"},{"key":"e_1_3_1_10_2","unstructured":"Stefan Gehrer. Highly efficient implementation of physical unclonable functions on FPGAs. The Technical University of Munich. https:\/\/mediatum.ub.tum.de\/doc\/1355406\/1355406.pdf."},{"key":"e_1_3_1_11_2"},{"key":"e_1_3_1_12_2"},{"key":"e_1_3_1_13_2"},{"key":"e_1_3_1_14_2","unstructured":"Xilinx. Artix-7 FPGAs data sheet: DC and AC switching characteristics (DS181). ([n. d.]) 64. https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds181_Artix_7_Data_Sheet.pdf."},{"key":"e_1_3_1_15_2"},{"key":"e_1_3_1_16_2"},{"key":"e_1_3_1_17_2"},{"key":"e_1_3_1_18_2"},{"key":"e_1_3_1_19_2"},{"key":"e_1_3_1_20_2"},{"key":"e_1_3_1_21_2"},{"key":"e_1_3_1_22_2"},{"key":"e_1_3_1_23_2","doi-asserted-by":"crossref","unstructured":"M. Slimani K. Benkalaia and L. Naviner. 2017. Analysis of ageing effects on ARTIX7 XILINX FPGA. Microelectronics Reliability 76\u201377 (2017) 168\u2013173.","DOI":"10.1016\/j.microrel.2017.07.006"},{"key":"e_1_3_1_24_2","doi-asserted-by":"crossref","unstructured":"R. S. Chakraborty I. Saha A. Palchaudhuri and G. K. Naik. 2013. Hardware trojan insertion by direct modification of FPGA configuration bitstream. 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