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Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture.<\/jats:p>","DOI":"10.1145\/3517808","type":"journal-article","created":{"date-parts":[[2022,4,20]],"date-time":"2022-04-20T11:59:53Z","timestamp":1650455993000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs"],"prefix":"10.1145","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3694-6861","authenticated-orcid":false,"given":"Dilip Kumar","family":"Maity","sequence":"first","affiliation":[{"name":"Indian Institute of Engineering Science and Technology, Howrah, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Surajit Kumar","family":"Roy","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering Science and Technology, Howrah, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chandan","family":"Giri","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering Science and Technology, Howrah, West Bengal, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,10,13]]},"reference":[{"key":"e_1_3_1_2_2","volume-title":"CMOS: Circuit Design, Layout, and Simulation","author":"Baker R. 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