{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:11:49Z","timestamp":1767262309463,"version":"3.41.0"},"reference-count":63,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2022,10,13]],"date-time":"2022-10-13T00:00:00Z","timestamp":1665619200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2022,10,31]]},"abstract":"<jats:p>\n            Today\u2019s intermittent computing systems operate by relying only on harvested energy accumulated in their tiny energy reservoirs, typically capacitors. An intermittent device dies due to a power failure when there is no energy in its capacitor and boots again when the harvested energy is sufficient to power its hardware components. Power failures prevent the forward progress of computation due to the frequent loss of computational state. To remedy this problem, intermittent computing systems comprise built-in fast non-volatile memories with high write endurance to store information that persists despite frequent power failures. However, the lack of design tools makes fast-prototyping these systems difficult. Even though FPGAs are common platforms for fast prototyping and behavioral verification of continuously powered architectures, they do not target prototyping intermittent computing systems. This article introduces a new FPGA-based framework, named NORM (\n            <jats:bold>N<\/jats:bold>\n            on-volatile mem\n            <jats:bold>OR<\/jats:bold>\n            y e\n            <jats:bold>M<\/jats:bold>\n            ulator), to emulate and verify the behavior of any intermittent computing system that exploits fast non-volatile memories. Our evaluation showed that NORM can be used to emulate and validate FeRAM-based transiently powered hardware architectures successfully.\n          <\/jats:p>","DOI":"10.1145\/3517812","type":"journal-article","created":{"date-parts":[[2022,3,23]],"date-time":"2022-03-23T14:43:44Z","timestamp":1648046624000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["NORM: An FPGA-based Non-volatile Memory Emulation Framework for Intermittent Computing"],"prefix":"10.1145","volume":"18","author":[{"given":"Simone","family":"Ruffini","sequence":"first","affiliation":[{"name":"University of Trento, Trento, Italy"}]},{"given":"Luca","family":"Caronti","sequence":"additional","affiliation":[{"name":"University of Trento, Trento, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9528-6923","authenticated-orcid":false,"given":"Kas\u0131m Sinan","family":"Y\u0131ld\u0131r\u0131m","sequence":"additional","affiliation":[{"name":"University of Trento, Trento, Italy"}]},{"given":"Davide","family":"Brunelli","sequence":"additional","affiliation":[{"name":"University of Trento, Trento, Italy"}]}],"member":"320","published-online":{"date-parts":[[2022,10,13]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2717782"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2547919"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1145\/3055031.3055082"},{"key":"e_1_3_1_5_2","doi-asserted-by":"crossref","unstructured":"Alexei Colin and Brandon Lucia. 2016. Chain: Tasks and channels for reliable intermittent programs. In Proceedings of the 2016 ACM SIGPLAN International Conference on Object-Oriented Programming Systems Languages and Applications . ACM 514\u2013530.","DOI":"10.1145\/2983990.2983995"},{"key":"e_1_3_1_6_2","unstructured":"Cypress. 2016. 1-Mbit (128K \u00d7 8) Quad SPI nvSRAM. Retrieved November 15 2021 from https:\/\/www.farnell.com\/datasheets\/2280496.pdf."},{"key":"e_1_3_1_7_2","unstructured":"Cypress. 2018. 256-Kbit (32 K \u00d7 8) SPI nvSRAM with Real Time Clock. Retrieved November 15 2021 from https:\/\/www.cypress.com\/file\/45216\/download."},{"key":"e_1_3_1_8_2","unstructured":"Cypress. 2019. FM22L16 4-Mbit (256K \u00d7 16) F-RAM. Retrieved November 15 2021 from https:\/\/www.cypress.com\/file\/136476\/download."},{"key":"e_1_3_1_9_2","unstructured":"Cypress. 2021. Excelon Ferroelectric-RAM (F-RAM): The Lowest-Power Nonvolatile Memory. Retrieved November 15 2021 from https:\/\/www.cypress.com\/products\/excelon-fram-memory#tabs-0-bottom_side-3."},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342227"},{"key":"e_1_3_1_11_2","unstructured":"Fujitsu. 2021. Memory ReRAM 8M (1024 K x 8) Bit SPI. (2021). Retrieved November 15 2021 from https:\/\/www.fujitsu.com\/jp\/group\/fsm\/en\/documents\/products\/reram\/lineup\/MB85AS8MT-DS501-00060-2v1-E.pdf."},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2013.404"},{"key":"e_1_3_1_13_2","first-page":"147","volume-title":"2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916)","author":"Gu Yizi","year":"2016","unstructured":"Yizi Gu, Yongpan Liu, Yiqun Wang, Hehe Li, and Huazhong Yang. 2016. NVPsim: A simulator for architecture explorations of nonvolatile processors. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC\u201916). IEEE, 147\u2013152."},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/2668332.2668382"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/3131672.3131699"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/3131672.3131673"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080238"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/2700249"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378476"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/RSP.2014.6966901"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2702741"},{"key":"e_1_3_1_22_2","article-title":"A survey of non-volatile main memory technologies: State-of-the-arts, practices, and future directions","volume":"2010","author":"Liu Haikun","year":"2020","unstructured":"Haikun Liu, Di Chen, Hai Jin, Xiaofei Liao, Bingsheng He, Kan Hu, and Yu Zhang. 2020. A survey of non-volatile main memory technologies: State-of-the-arts, practices, and future directions. CoRR abs\/2010.04406 (2020). arXiv:2010.04406. https:\/\/arxiv.org\/abs\/2010.04406.","journal-title":"CoRR"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417918"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1145\/2813885.2737978"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.35"},{"key":"e_1_3_1_26_2","first-page":"526","volume-title":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA\u201915)","author":"Ma Kaisheng","year":"2015","unstructured":"Kaisheng Ma, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yongpan Liu, Jack Sampson, Yuan Xie, and Vijaykrishnan Narayanan. 2015. Architecture exploration for ambient energy harvesting nonvolatile processors. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA\u201915). IEEE, 526\u2013537."},{"key":"e_1_3_1_27_2","article-title":"Alpaca: Intermittent execution without checkpoints","author":"Maeng Kiwan","year":"2019","unstructured":"Kiwan Maeng, Alexei Colin, and Brandon Lucia. 2019. Alpaca: Intermittent execution without checkpoints. arXiv preprint arXiv:1909.06951 (2019).","journal-title":"arXiv preprint arXiv:1909.06951"},{"key":"e_1_3_1_28_2","first-page":"129","volume-title":"13th USENIX Symposium on Operating Systems Design and Implementation (OSDI\u201918)","author":"Maeng Kiwan","year":"2018","unstructured":"Kiwan Maeng and Brandon Lucia. 2018. Adaptive dynamic checkpointing for safe efficient intermittent computing. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI\u201918). 129\u2013144."},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3385998"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/3360285"},{"key":"e_1_3_1_31_2","unstructured":"Micron. 2005. P8P Parallel Phase Change Memory (PCM). Retrieved November 15 2021 from https:\/\/www.digchip.com\/datasheets\/parts\/datasheet\/297\/NP8P128A13BSM60E-pdf.php."},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/3362053.3363491"},{"key":"e_1_3_1_33_2","article-title":"Github Repo","year":"2021","unstructured":"NORM. 2021. Github Repo. Retrieved February 15, 2021, from https:\/\/github.com\/simoneruffini\/NORM.","journal-title":"https:\/\/github.com\/simoneruffini\/NORM"},{"key":"e_1_3_1_34_2","unstructured":"NXP. 2007. 256K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM. Retrieved November 15 2021 from https:\/\/www.nxp.com\/docs\/en\/data-sheet\/MR2A16A.pdf."},{"key":"e_1_3_1_35_2","first-page":"1","volume-title":"2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA\u201919)","author":"Omori Yu","year":"2019","unstructured":"Yu Omori and Keiji Kimura. 2019. Performance evaluation on NVMM emulator employing fine-grain delay injection. In 2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA\u201919). IEEE, 1\u20136."},{"key":"e_1_3_1_36_2","article-title":"Voltage traces","year":"2021","unstructured":"PERSISTLab. 2021. Voltage traces. Retrieved January 31, 2021, from https:\/\/github.com\/PERSISTLab\/BatterylessSim\/blob\/master\/traces\/README.","journal-title":"https:\/\/github.com\/PERSISTLab\/BatterylessSim\/blob\/master\/traces\/README"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1145\/2618128.2618136"},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1145\/1961295.1950386"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314583"},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2008.925019"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2822697"},{"key":"e_1_3_1_43_2","first-page":"339","volume-title":"2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI\u201918)","author":"Shi Xin","year":"2018","unstructured":"Xin Shi, Tongda Wu, Keni Qiu, Huazhong Yang, and Yongpan Liu. 2018. Time stamp based scheduling for energy harvesting systems with hybrid nonvolatile hardware support. In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI\u201918). IEEE, 339\u2013344."},{"key":"e_1_3_1_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS48437.2020.00046"},{"key":"e_1_3_1_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2616905"},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927131"},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2995854"},{"key":"e_1_3_1_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2847600"},{"key":"e_1_3_1_49_2","unstructured":"Avalanche Technology.2021. Data Endurance Retention and Field Immunity in STT-MRAM. Retrieved November 15 2021 from https:\/\/www.avalanche-technology.com\/wp-content\/uploads\/AN000002-Avalanche-STT-MRAM-Device-Characteristics-and-Capabilities.pdf."},{"key":"e_1_3_1_50_2","unstructured":"Texas Instruments. 2018. MSP430FR5969 LaunchPad Development Kit. Retrieved November 15 2021 from http:\/\/www.ti.com\/tool\/MSP-EXP430FR5969."},{"key":"e_1_3_1_51_2","article-title":"FRAM FAQs","author":"Inc. Texas Instruments,","year":"2014","unstructured":"Texas Instruments, Inc.2014. FRAM FAQs. Retrieved November 15, 2021, from https:\/\/www.ti.com\/lit\/pdf\/slat151.","journal-title":"https:\/\/www.ti.com\/lit\/pdf\/slat151"},{"key":"e_1_3_1_52_2","doi-asserted-by":"publisher","DOI":"10.1145\/3417308.3430269"},{"key":"e_1_3_1_53_2","first-page":"17","volume-title":"12th USENIX Symposium on Operating Systems Design and Implementation (OSDI\u201916)","author":"Woude Joel Van Der","year":"2016","unstructured":"Joel Van Der Woude and Matthew Hicks. 2016. Intermittent computation without hardware support or programmer intervention. In 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI\u201916). 17\u201332."},{"key":"e_1_3_1_54_2","unstructured":"Various authors. 2021. Retrieved November 15 2021 from https:\/\/en.wikipedia.org\/wiki\/Ferroelectric_RAM."},{"key":"e_1_3_1_55_2","unstructured":"Various authors. 2021. Retrieved November 15 2021 from https:\/\/en.wikipedia.org\/wiki\/Magnetoresistive_RAM."},{"key":"e_1_3_1_56_2","unstructured":"Various authors. 2021. Retrieved November 15 2021 from https:\/\/en.wikipedia.org\/wiki\/Resistive_random-access_memory."},{"key":"e_1_3_1_57_2","unstructured":"Various authors. 2021. Retrieved November 15 2021 from https:\/\/en.wikipedia.org\/wiki\/Phase-change_memory."},{"key":"e_1_3_1_58_2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2012.6341281"},{"key":"e_1_3_1_59_2","doi-asserted-by":"publisher","DOI":"10.1145\/3279755.3279756"},{"key":"e_1_3_1_60_2","article-title":"Vivado Design Suite","year":"2021","unstructured":"Xilinx. 2021. Vivado Design Suite. Retrieved January 31, 2021, from https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html.","journal-title":"https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html"},{"key":"e_1_3_1_61_2","article-title":"Vivado Simulator","year":"2021","unstructured":"Xilinx. 2021. Vivado Simulator. Retrieved January 31, 2021, from https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/simulator.html.","journal-title":"https:\/\/www.xilinx.com\/products\/design-tools\/vivado\/simulator.html"},{"key":"e_1_3_1_62_2","unstructured":"Xilinx. December 9 2019. Block Memory Generator v8.4. https:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/blk_mem_gen\/v8_4\/pg058-blk-mem-gen.pdf."},{"key":"e_1_3_1_63_2","doi-asserted-by":"publisher","DOI":"10.1145\/3274783.3274837"},{"key":"e_1_3_1_64_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2715346"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3517812","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3517812","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:49:05Z","timestamp":1750182545000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3517812"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,13]]},"references-count":63,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2022,10,31]]}},"alternative-id":["10.1145\/3517812"],"URL":"https:\/\/doi.org\/10.1145\/3517812","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2022,10,13]]},"assertion":[{"value":"2021-08-02","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-02-11","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-10-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}