{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,23]],"date-time":"2026-07-23T20:13:11Z","timestamp":1784837591251,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":74,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,9]],"date-time":"2022-06-09T00:00:00Z","timestamp":1654732800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,9]]},"DOI":"10.1145\/3519939.3523719","type":"proceedings-article","created":{"date-parts":[[2022,6,2]],"date-time":"2022-06-02T21:05:05Z","timestamp":1654203905000},"page":"888-902","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":23,"title":["Lasagne: a static binary translator for weak memory model architectures"],"prefix":"10.1145","author":[{"given":"Rodrigo C. O.","family":"Rocha","sequence":"first","affiliation":[{"name":"University of Edinburgh, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dennis","family":"Sprokholt","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Netherlands"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Martin","family":"Fink","sequence":"additional","affiliation":[{"name":"TU Munich, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Redha","family":"Gouicem","sequence":"additional","affiliation":[{"name":"TU Munich, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tom","family":"Spink","sequence":"additional","affiliation":[{"name":"University of St. Andrews, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Soham","family":"Chakraborty","sequence":"additional","affiliation":[{"name":"Delft University of Technology, Netherlands"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pramod","family":"Bhatotia","sequence":"additional","affiliation":[{"name":"TU Munich, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,6,9]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26850-7_3"},{"key":"e_1_3_2_2_2_1","unstructured":"Agda Development Team. 2021. Agda 2.6.2 documentation. https:\/\/agda.readthedocs.io\/en\/v2.6.2\/  Agda Development Team. 2021. Agda 2.6.2 documentation. https:\/\/agda.readthedocs.io\/en\/v2.6.2\/"},{"key":"e_1_3_2_2_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2994593"},{"key":"e_1_3_2_2_4_1","unstructured":"Jade Alglave and Luc Maranget. 2022. herd7 consistency model simulator. http:\/\/diy.inria.fr\/www\/  Jade Alglave and Luc Maranget. 2022. herd7 consistency model simulator. http:\/\/diy.inria.fr\/www\/"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2627752"},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1145\/360018.360025"},{"key":"e_1_3_2_2_7_1","unstructured":"Apple. 2021. Rosetta 2 on a Mac with Apple silicon. https:\/\/support.apple.com\/fr-fr\/guide\/security\/secebb113be1\/web  Apple. 2021. Rosetta 2 on a Mac with Apple silicon. https:\/\/support.apple.com\/fr-fr\/guide\/security\/secebb113be1\/web"},{"key":"e_1_3_2_2_8_1","unstructured":"Apple. 2022. Porting Your macOS Apps to Apple Silicon. https:\/\/developer.apple.com\/documentation\/apple-silicon\/porting-your-macos-apps-to-apple-silicon  Apple. 2022. Porting Your macOS Apps to Apple Silicon. https:\/\/developer.apple.com\/documentation\/apple-silicon\/porting-your-macos-apps-to-apple-silicon"},{"key":"e_1_3_2_2_9_1","unstructured":"avast. 2022. A retargetable machine-code decompiler based on LLVM. https:\/\/github.com\/avast\/retdec  avast. 2022. A retargetable machine-code decompiler based on LLVM. https:\/\/github.com\/avast\/retdec"},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2103621.2103717"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/1926385.1926394"},{"key":"e_1_3_2_2_12_1","unstructured":"Lifting Bits. 2022. Framework for lifting x86 amd64 and aarch64 program binaries to LLVM bitcode. https:\/\/github.com\/lifting-bits\/mcsema  Lifting Bits. 2022. Framework for lifting x86 amd64 and aarch64 program binaries to LLVM bitcode. https:\/\/github.com\/lifting-bits\/mcsema"},{"key":"e_1_3_2_2_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-37036-6_29"},{"key":"e_1_3_2_2_14_1","unstructured":"Ahmed Bougacha. 2022. Binary Translator to LLVM IR. https:\/\/github.com\/repzret\/dagger  Ahmed Bougacha. 2022. Binary Translator to LLVM IR. https:\/\/github.com\/repzret\/dagger"},{"key":"e_1_3_2_2_15_1","unstructured":"Soham Chakraborty. 2021. Robustness between Weak Memory Models. In FMCAD\u201921. 173\u2013182.  Soham Chakraborty. 2021. Robustness between Weak Memory Models. In FMCAD\u201921. 173\u2013182."},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/2854038.2854051"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2017.7863732"},{"key":"e_1_3_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3290383"},{"key":"e_1_3_2_2_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2017.7863741"},{"key":"e_1_3_2_2_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3475061.3475081"},{"key":"e_1_3_2_2_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/357094.357098"},{"key":"e_1_3_2_2_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2011.102"},{"key":"e_1_3_2_2_23_1","unstructured":"Andrei Frumusanu. 2020. Amazon\u2019s Arm-based Graviton2 Against AMD and Intel: Comparing Cloud Compute \u2013 Anandtech. https:\/\/www.anandtech.com\/show\/15578\/cloud-clash-amazon-graviton2-arm-against-intel-and-amd  Andrei Frumusanu. 2020. Amazon\u2019s Arm-based Graviton2 Against AMD and Intel: Comparing Cloud Compute \u2013 Anandtech. https:\/\/www.anandtech.com\/show\/15578\/cloud-clash-amazon-graviton2-arm-against-intel-and-amd"},{"key":"e_1_3_2_2_24_1","doi-asserted-by":"publisher","DOI":"10.1002\/spe.2573"},{"key":"e_1_3_2_2_25_1","doi-asserted-by":"publisher","DOI":"10.1002\/spe.2394"},{"key":"e_1_3_2_2_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2259016.2259030"},{"key":"e_1_3_2_2_27_1","doi-asserted-by":"publisher","DOI":"10.23638\/LMCS-15(1:33)2019"},{"key":"e_1_3_2_2_28_1","unstructured":"Saagar Jha. 2020. TSOEnabler \u2013 Kernel extension that enables TSO for Apple silicon processes. https:\/\/github.com\/saagarjha\/TSOEnabler  Saagar Jha. 2020. TSOEnabler \u2013 Kernel extension that enables TSO for Apple silicon processes. https:\/\/github.com\/saagarjha\/TSOEnabler"},{"key":"e_1_3_2_2_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/3093333.3009850"},{"key":"e_1_3_2_2_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2813885.2738005"},{"key":"e_1_3_2_2_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3314221.3314604"},{"key":"e_1_3_2_2_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3062341.3062352"},{"key":"e_1_3_2_2_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675439"},{"key":"e_1_3_2_2_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3062341.3062343"},{"key":"e_1_3_2_2_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2000.888336"},{"key":"e_1_3_2_2_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3386010"},{"key":"e_1_3_2_2_37_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-22306-8_10"},{"key":"e_1_3_2_2_38_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36742-7_24"},{"key":"e_1_3_2_2_39_1","doi-asserted-by":"publisher","DOI":"10.1145\/2345156.2254115"},{"key":"e_1_3_2_2_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3475061.3475081"},{"key":"e_1_3_2_2_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2737924.2737965"},{"key":"e_1_3_2_2_42_1","unstructured":"QEMU. [n. d.]. the FAST! processor emulator. https:\/\/www.qemu.org\/  QEMU. [n. d.]. the FAST! processor emulator. https:\/\/www.qemu.org\/"},{"key":"e_1_3_2_2_43_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750378"},{"key":"e_1_3_2_2_44_1","doi-asserted-by":"publisher","DOI":"10.1145\/3434285"},{"key":"e_1_3_2_2_45_1","doi-asserted-by":"publisher","DOI":"10.1145\/364995.365000"},{"key":"e_1_3_2_2_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302516.3307357"},{"key":"e_1_3_2_2_47_1","doi-asserted-by":"publisher","DOI":"10.1145\/2499370.2491967"},{"key":"e_1_3_2_2_48_1","doi-asserted-by":"publisher","DOI":"10.1145\/2908080.2908109"},{"key":"e_1_3_2_2_49_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446748"},{"key":"e_1_3_2_2_50_1","doi-asserted-by":"publisher","DOI":"10.4230\/LIPIcs.ECOOP.2015.445"},{"key":"e_1_3_2_2_51_1","doi-asserted-by":"publisher","DOI":"10.1145\/3290382"},{"key":"e_1_3_2_2_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2019.8661192"},{"key":"e_1_3_2_2_53_1","doi-asserted-by":"publisher","DOI":"10.1145\/3243176.3243189"},{"key":"e_1_3_2_2_54_1","doi-asserted-by":"publisher","DOI":"10.1145\/3158107"},{"key":"e_1_3_2_2_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346181"},{"key":"e_1_3_2_2_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO53902.2022.9741256"},{"key":"e_1_3_2_2_57_1","doi-asserted-by":"publisher","DOI":"10.1145\/3461648.3463852"},{"key":"e_1_3_2_2_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2019.8661174"},{"key":"e_1_3_2_2_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/3385412.3386030"},{"key":"e_1_3_2_2_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254102"},{"key":"e_1_3_2_2_61_1","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993534"},{"key":"e_1_3_2_2_62_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-70592-5_3"},{"key":"e_1_3_2_2_63_1","unstructured":"Jaroslav Sevcik and Peter Sewell. 2016. C\/C++11 mappings to processors. https:\/\/www.cl.cam.ac.uk\/ pes20\/cpp\/cpp0xmappings.html  Jaroslav Sevcik and Peter Sewell. 2016. C\/C++11 mappings to processors. https:\/\/www.cl.cam.ac.uk\/ pes20\/cpp\/cpp0xmappings.html"},{"key":"e_1_3_2_2_64_1","unstructured":"Agam Shah. 2021. We\u2019re closing the gap with Arm and x86 claims SiFive: New RISC-V CPU core for PCs servers mobile incoming \u2013 The Register. https:\/\/www.theregister.com\/2021\/10\/21\/sifive_riscv_cpu\/  Agam Shah. 2021. We\u2019re closing the gap with Arm and x86 claims SiFive: New RISC-V CPU core for PCs servers mobile incoming \u2013 The Register. https:\/\/www.theregister.com\/2021\/10\/21\/sifive_riscv_cpu\/"},{"key":"e_1_3_2_2_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/42190.42277"},{"key":"e_1_3_2_2_66_1","doi-asserted-by":"publisher","DOI":"10.1145\/2380403.2380419"},{"key":"e_1_3_2_2_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302516.3307357"},{"key":"e_1_3_2_2_68_1","doi-asserted-by":"publisher","DOI":"10.1145\/357153.357155"},{"key":"e_1_3_2_2_69_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO51591.2021.9370308"},{"key":"e_1_3_2_2_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/2676726.2676995"},{"key":"e_1_3_2_2_71_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941583"},{"key":"e_1_3_2_2_72_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316482.3326354"},{"key":"e_1_3_2_2_73_1","volume-title":"Workshop on Optimizations for DSP and Embedded Systems.","author":"Chen Jiunn","year":"2008","unstructured":"Jiunn yeu Chen , Wuu Yang , Charlie Su , and Wei Chung Hsu . 2008 . A static binary translator for efficient migration of ARM-based applications . In Workshop on Optimizations for DSP and Embedded Systems. Jiunn yeu Chen, Wuu Yang, Charlie Su, and Wei Chung Hsu. 2008. A static binary translator for efficient migration of ARM-based applications. In Workshop on Optimizations for DSP and Embedded Systems."},{"key":"e_1_3_2_2_74_1","doi-asserted-by":"publisher","DOI":"10.1145\/3339186.3339192"}],"event":{"name":"PLDI '22: 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation","location":"San Diego CA USA","acronym":"PLDI '22","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"]},"container-title":["Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3519939.3523719","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3519939.3523719","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T18:10:30Z","timestamp":1750183830000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3519939.3523719"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,9]]},"references-count":74,"alternative-id":["10.1145\/3519939.3523719","10.1145\/3519939"],"URL":"https:\/\/doi.org\/10.1145\/3519939.3523719","relation":{},"subject":[],"published":{"date-parts":[[2022,6,9]]},"assertion":[{"value":"2022-06-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}