{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,12]],"date-time":"2025-07-12T01:22:21Z","timestamp":1752283341877,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":49,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T00:00:00Z","timestamp":1656374400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Ministerio de Ciencia, Innovaci\u00f3n y Universidades and the European ERDF","award":["RTI2018-098156-B-C51"],"award-info":[{"award-number":["RTI2018-098156-B-C51"]}]},{"name":"Dept. of Science, University, and Knowledge Society, Government of Aragon","award":["gaZ: T5820R research group"],"award-info":[{"award-number":["gaZ: T5820R research group"]}]},{"name":"Agencia Estatal de Investigaci\u00f3n (AEI)","award":["PID2019-105660RB-C21\/AEI\/10.13039\/501100011033"],"award-info":[{"award-number":["PID2019-105660RB-C21\/AEI\/10.13039\/501100011033"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,28]]},"DOI":"10.1145\/3524059.3532383","type":"proceedings-article","created":{"date-parts":[[2022,6,16]],"date-time":"2022-06-16T16:13:11Z","timestamp":1655395991000},"page":"1-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Fast-track cache"],"prefix":"10.1145","author":[{"given":"Hugo","family":"T\u00e1rrega","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alejandro","family":"Valero","sequence":"additional","affiliation":[{"name":"Universidad de Zaragoza, Zaragoza, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vicente","family":"Lorente","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Salvador","family":"Petit","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Julio","family":"Sahuquillo","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Valencia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,6,28]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2006. Standard Performance Evaluation Corporation available online at http:\/\/www.spec.org\/cpu2006\/.  2006. Standard Performance Evaluation Corporation available online at http:\/\/www.spec.org\/cpu2006\/."},{"volume-title":"Proceedings of the 50th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 331--342","author":"Archer S.","key":"e_1_3_2_1_2_1","unstructured":"S. Archer , G. Mappouras , R. Calderbank , and D. J. Sorin . 2020. Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory . In Proceedings of the 50th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 331--342 . S. Archer, G. Mappouras, R. Calderbank, and D. J. Sorin. 2020. Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. In Proceedings of the 50th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 331--342."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324558"},{"volume-title":"Proceedings of the 33rd IEEE International Conference on Computer Design. 427--430","author":"Atoofian E.","key":"e_1_3_2_1_4_1","unstructured":"E. Atoofian and A. Saghir . 2015. Shift-Aware Racetrack Memory . In Proceedings of the 33rd IEEE International Conference on Computer Design. 427--430 . E. Atoofian and A. Saghir. 2015. Shift-Aware Racetrack Memory. In Proceedings of the 33rd IEEE International Conference on Computer Design. 427--430."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.2018.2807480"},{"volume-title":"Proceedings of the IEEE International Symposium on Information Theory. 2924--2929","author":"Chee Y. M.","key":"e_1_3_2_1_6_1","unstructured":"Y. M. Chee , A. Vardy , V. K. Vu , and E. Yaakobi . 2021. Coding for Transverse-Reads in Domain Wall Memories . In Proceedings of the IEEE International Symposium on Information Theory. 2924--2929 . Y. M. Chee, A. Vardy, V. K. Vu, and E. Yaakobi. 2021. Coding for Transverse-Reads in Domain Wall Memories. In Proceedings of the IEEE International Symposium on Information Theory. 2924--2929."},{"volume-title":"Proceedings of the 23rd Asia and South Pacific Design Automation Conference. 221--226","author":"Chen F.","key":"e_1_3_2_1_7_1","unstructured":"F. Chen , Z. Li , W. Kang , W. Zhao , H. Li , and Y. Chen . 2018. Process Variation Aware Data Management for Magnetic Skyrmions Racetrack Memory . In Proceedings of the 23rd Asia and South Pacific Design Automation Conference. 221--226 . F. Chen, Z. Li, W. Kang, W. Zhao, H. Li, and Y. Chen. 2018. Process Variation Aware Data Management for Magnetic Skyrmions Racetrack Memory. In Proceedings of the 23rd Asia and South Pacific Design Automation Conference. 221--226."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2537400"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3358199"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2968081"},{"volume-title":"Proceedings of the IEEE International Parallel and Distributed Processing Symposium. 273--282","author":"Colaso A.","key":"e_1_3_2_1_11_1","unstructured":"A. Colaso , P. Prieto , P. Abad , J. A. Gregorio , and V. Puente . 2019. Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms . In Proceedings of the IEEE International Parallel and Distributed Processing Symposium. 273--282 . A. Colaso, P. Prieto, P. Abad, J. A. Gregorio, and V. Puente. 2019. Architecting Racetrack Memory Preshift through Pattern-Based Prediction Mechanisms. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium. 273--282."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2021.3122225"},{"volume-title":"Proceedings of the IEEE Symposium on VLSI Technology. 230--231","author":"Fukami S.","key":"e_1_3_2_1_13_1","unstructured":"S. Fukami , T. Suzuki , K. Nagahara , N. Ohshima , Y. Ozaki , S. Saito , R. Nebashi , N. Sakimura , H. Honjo , K. Mori , C. Igarashi , S. Miura , N. Ishiwata , and T. Sugibayashi . 2009. Low-Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM . In Proceedings of the IEEE Symposium on VLSI Technology. 230--231 . S. Fukami, T. Suzuki, K. Nagahara, N. Ohshima, Y. Ozaki, S. Saito, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, C. Igarashi, S. Miura, N. Ishiwata, and T. Sugibayashi. 2009. Low-Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM. In Proceedings of the IEEE Symposium on VLSI Technology. 230--231."},{"volume-title":"Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 1502--1507","author":"Khan A. A.","key":"e_1_3_2_1_14_1","unstructured":"A. A. Khan , A. Goens , F. Hameed , and J. Castrillon . 2020. Generalized Data Placement Strategies for Racetrack Memories . In Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 1502--1507 . A. A. Khan, A. Goens, F. Hameed, and J. Castrillon. 2020. Generalized Data Placement Strategies for Racetrack Memories. In Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 1502--1507."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"A. A. Khan F. Hameed R. Bl\u00e4sing S. S. P. Parkin and J. Castrillon. 2019. ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0. ACM Transactions on Architecture and Code Optimization 16 4 Article 56 (2019) 23 pages.  A. A. Khan F. Hameed R. Bl\u00e4sing S. S. P. Parkin and J. Castrillon. 2019. ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0. ACM Transactions on Architecture and Code Optimization 16 4 Article 56 (2019) 23 pages.","DOI":"10.1145\/3372489"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012266"},{"volume-title":"Proceedings of the IFIP\/IEEE International Conference on Very Large Scale Integration. 1--6.","author":"Larimi S. S. N.","key":"e_1_3_2_1_17_1","unstructured":"S. S. N. Larimi , M. Kamal , A. Afzali-Kusha , and H. Mahmoodi . 2016. Power and Energy Reduction of Racetrack-based Caches by Exploiting Shared Shift Operations . In Proceedings of the IFIP\/IEEE International Conference on Very Large Scale Integration. 1--6. S. S. N. Larimi, M. Kamal, A. Afzali-Kusha, and H. Mahmoodi. 2016. Power and Energy Reduction of Racetrack-based Caches by Exploiting Shared Shift Operations. In Proceedings of the IFIP\/IEEE International Conference on Very Large Scale Integration. 1--6."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA\/IUCC.2017.00061"},{"volume-title":"Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium. 1--5.","author":"Mao H.","key":"e_1_3_2_1_19_1","unstructured":"H. Mao , C. Zhang , G. Sun , and J. Shu . 2015. Exploring Data Placement in Racetrack Memory Based Scratchpad Memory . In Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium. 1--5. H. Mao, C. Zhang, G. Sun, and J. Shu. 2015. Exploring Data Placement in Racetrack Memory Based Scratchpad Memory. In Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium. 1--5."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2690855"},{"volume-title":"Proceedings of the 49th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 1--12","author":"Mappouras G.","key":"e_1_3_2_1_21_1","unstructured":"G. Mappouras , A. Vahid , R. Calderbank , and D. J. Sorin . 2019. GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors . In Proceedings of the 49th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 1--12 . G. Mappouras, A. Vahid, R. Calderbank, and D. J. Sorin. 2019. GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors. In Proceedings of the 49th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 1--12."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.3390\/jlpea7030023"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2397876"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2437283"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2391185"},{"volume-title":"Proceedings of the 49th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 375--387","author":"Ollivier S.","key":"e_1_3_2_1_26_1","unstructured":"S. Ollivier , D. Kline , R. Kawsher , R. Melhem , S. Banja , and A. K. Jones . 2019. Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories . In Proceedings of the 49th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 375--387 . S. Ollivier, D. Kline, R. Kawsher, R. Melhem, S. Banja, and A. K. Jones. 2019. Leveraging Transverse Reads to Correct Alignment Faults in Domain Wall Memories. In Proceedings of the 49th Annual IEEE\/IFIP International Conference on Dependable Systems and Networks. 375--387."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"S. S. P. Parkin M. Hayashi and L. Thomas. 2008. Magnetic Domain-Wall Racetrack Memory. Science 320 5873 (2008) 190--194.  S. S. P. Parkin M. Hayashi and L. Thomas. 2008. Magnetic Domain-Wall Racetrack Memory. Science 320 5873 (2008) 190--194.","DOI":"10.1126\/science.1145799"},{"volume-title":"Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 181--186","author":"Ranjan A.","key":"e_1_3_2_1_28_1","unstructured":"A. Ranjan , S. G. Ramasubramanian , R. Venkatesan , V. Pai , K. Roy , and A. Raghunathan . 2015. DyReCTape: A Dynamically Reconfigurable Cache using Domain Wall Memory Tapes . In Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 181--186 . A. Ranjan, S. G. Ramasubramanian, R. Venkatesan, V. Pai, K. Roy, and A. Raghunathan. 2015. DyReCTape: A Dynamically Reconfigurable Cache using Domain Wall Memory Tapes. In Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 181--186."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2020.3014091"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3399670"},{"key":"e_1_3_2_1_31_1","first-page":"102","article-title":"Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system","volume":"117","author":"Sha E. H.-M.","year":"2021","unstructured":"E. H.-M. Sha , M. Xu , S. Gu , and Q. Zhuge . 2021 . Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system . Elsevier Journal of Systems Architecture 117 (2021), 102 -- 145 . E. H.-M. Sha, M. Xu, S. Gu, and Q. Zhuge. 2021. Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system. Elsevier Journal of Systems Architecture 117 (2021), 102--145.","journal-title":"Elsevier Journal of Systems Architecture"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2020.3011447"},{"volume-title":"Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design. 263--266","author":"Sun Z.","key":"e_1_3_2_1_33_1","unstructured":"Z. Sun , X. Bi , A. K. Jones , and H. Li . 2014. Design Exploration of Racetrack Lower-Level Caches . In Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design. 263--266 . Z. Sun, X. Bi, A. K. Jones, and H. Li. 2014. Design Exploration of Racetrack Lower-Level Caches. In Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design. 263--266."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2360545"},{"key":"e_1_3_2_1_35_1","unstructured":"S. Thoziyoor N. Muralimanohar J.H. Ahn and N. P. Jouppi. 2008. CACTI 5.1. HP Development Company Palo Alto CA USA. Technical Report HPL-2008-20 (2008).  S. Thoziyoor N. Muralimanohar J.H. Ahn and N. P. Jouppi. 2008. CACTI 5.1. HP Development Company Palo Alto CA USA. Technical Report HPL-2008-20 (2008)."},{"volume-title":"Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. 335--344","author":"Ubal R.","key":"e_1_3_2_1_36_1","unstructured":"R. Ubal , B. Jang , P. Mistry , D. Schaa , and D. Kaeli . 2012. Multi2Sim: A Simulation Framework for CPU-GPU Computing . In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. 335--344 . R. Ubal, B. Jang, P. Mistry, D. Schaa, and D. Kaeli. 2012. Multi2Sim: A Simulation Framework for CPU-GPU Computing. In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. 335--344."},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2506581"},{"volume-title":"Proceedings of the ACM\/IEEE 41st International Symposium on Computer Architecture. 253--264","author":"Venkatesan R.","key":"e_1_3_2_1_38_1","unstructured":"R. Venkatesan , S. G. Ramasubramanian , S. Venkataramani , K. Roy , and A. Raghunathan . 2014. STAG: Spintronic-Tape Architecture for GPGPU Cache Hierarchies . In Proceedings of the ACM\/IEEE 41st International Symposium on Computer Architecture. 253--264 . R. Venkatesan, S. G. Ramasubramanian, S. Venkataramani, K. Roy, and A. Raghunathan. 2014. STAG: Spintronic-Tape Architecture for GPGPU Cache Hierarchies. In Proceedings of the ACM\/IEEE 41st International Symposium on Computer Architecture. 253--264."},{"volume-title":"Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 1825--1830","author":"Venkatesan R.","key":"e_1_3_2_1_39_1","unstructured":"R. Venkatesan , M. Sharad , K. Roy , and A. Raghunathan . 2013. DWM-TAPESTRI - An Energy Efficient All-Spin Cache using Domain wall Shift based Writes . In Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 1825--1830 . R. Venkatesan, M. Sharad, K. Roy, and A. Raghunathan. 2013. DWM-TAPESTRI - An Energy Efficient All-Spin Cache using Domain wall Shift based Writes. In Proceedings of the Design, Automation, and Test in Europe Conference Exhibition. 1825--1830."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/2723165"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2866932"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3045433"},{"volume-title":"Proceedings of the 21st Asia and South Pacific Design Automation Conference. 25--30","author":"Wang S.","key":"e_1_3_2_1_43_1","unstructured":"S. Wang , Y. Liang , C. Zhang , X. Xie , G. Sun , Y. Liu , Y. Wang , and X. Li . 2016. Performance-centric Register File Design for GPUs using Racetrack Memory . In Proceedings of the 21st Asia and South Pacific Design Automation Conference. 25--30 . S. Wang, Y. Liang, C. Zhang, X. Xie, G. Sun, Y. Liu, Y. Wang, and X. Li. 2016. Performance-centric Register File Design for GPUs using Racetrack Memory. In Proceedings of the 21st Asia and South Pacific Design Automation Conference. 25--30."},{"volume-title":"Proceedings of the IEEE\/ACM International Symposium on Nanoscale Architectures. 23--24","author":"Wang X.","key":"e_1_3_2_1_44_1","unstructured":"X. Wang , C. Zhang , X. Zhang , and G. Sun . 2016. np-ECC: Nonadjacent Position Error Correction Code for Racetrack Memory . In Proceedings of the IEEE\/ACM International Symposium on Nanoscale Architectures. 23--24 . X. Wang, C. Zhang, X. Zhang, and G. Sun. 2016. np-ECC: Nonadjacent Position Error Correction Code for Racetrack Memory. In Proceedings of the IEEE\/ACM International Symposium on Nanoscale Architectures. 23--24."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2016.2536020"},{"volume-title":"Proceedings of the 20th Asia and South Pacific Design Automation Conference. 417--422","author":"Xu H.","key":"e_1_3_2_1_46_1","unstructured":"H. Xu , Y. Li , R. Melhem , and A. K. Jones . 2015. Multilane Racetrack Caches: Improving Efficiency Through Compression and Independent Shifting . In Proceedings of the 20th Asia and South Pacific Design Automation Conference. 417--422 . H. Xu, Y. Li, R. Melhem, and A. K. Jones. 2015. Multilane Racetrack Caches: Improving Efficiency Through Compression and Independent Shifting. In Proceedings of the 20th Asia and South Pacific Design Automation Conference. 417--422."},{"volume-title":"Proceedings of the 20th Asia and South Pacific Design Automation Conference. 100--105","author":"Zhang C.","key":"e_1_3_2_1_47_1","unstructured":"C. Zhang , G. Sun , W. Zhang , F. Mi , H. Li , and W. Zhao . 2015. Quantitative Modeling of Racetrack Memory, a Tradeoff among Area, Performance, and Power . In Proceedings of the 20th Asia and South Pacific Design Automation Conference. 100--105 . C. Zhang, G. Sun, W. Zhang, F. Mi, H. Li, and W. Zhao. 2015. Quantitative Modeling of Racetrack Memory, a Tradeoff among Area, Performance, and Power. In Proceedings of the 20th Asia and South Pacific Design Automation Conference. 100--105."},{"volume-title":"Proceedings of the ACM\/IEEE 42nd Annual International Symposium on Computer Architecture. 694--706","author":"Zhang C.","key":"e_1_3_2_1_48_1","unstructured":"C. Zhang , G. Sun , X. Zhang , W. Zhang , W. Zhao , T. Wang , Y. Liang , Y. Liu , Y. Wang , and J. Shu . 2015. Hi-Fi Playback: Tolerating Position Errors in Shift Operations of Racetrack Memory . In Proceedings of the ACM\/IEEE 42nd Annual International Symposium on Computer Architecture. 694--706 . C. Zhang, G. Sun, X. Zhang, W. Zhang, W. Zhao, T. Wang, Y. Liang, Y. Liu, Y. Wang, and J. Shu. 2015. Hi-Fi Playback: Tolerating Position Errors in Shift Operations of Racetrack Memory. In Proceedings of the ACM\/IEEE 42nd Annual International Symposium on Computer Architecture. 694--706."},{"volume-title":"Proceedings of the 33rd IEEE International Conference on Computer Design. 157--163","author":"Zhang X.","key":"e_1_3_2_1_49_1","unstructured":"X. Zhang , L. Zhao , Y. Zhang , and J. Yang . 2015. Exploit Common Source-Line to Construct Energy Efficient Domain Wall Memory Based Caches . In Proceedings of the 33rd IEEE International Conference on Computer Design. 157--163 . X. Zhang, L. Zhao, Y. Zhang, and J. Yang. 2015. Exploit Common Source-Line to Construct Energy Efficient Domain Wall Memory Based Caches. In Proceedings of the 33rd IEEE International Conference on Computer Design. 157--163."}],"event":{"name":"ICS '22: 2022 International Conference on Supercomputing","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture"],"location":"Virtual Event","acronym":"ICS '22"},"container-title":["Proceedings of the 36th ACM International Conference on Supercomputing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3524059.3532383","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3524059.3532383","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:30:38Z","timestamp":1750188638000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3524059.3532383"}},"subtitle":["a huge racetrack memory L1 data cache"],"short-title":[],"issued":{"date-parts":[[2022,6,28]]},"references-count":49,"alternative-id":["10.1145\/3524059.3532383","10.1145\/3524059"],"URL":"https:\/\/doi.org\/10.1145\/3524059.3532383","relation":{},"subject":[],"published":{"date-parts":[[2022,6,28]]},"assertion":[{"value":"2022-06-28","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}