{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T23:23:53Z","timestamp":1774653833442,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T00:00:00Z","timestamp":1654473600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,6]]},"DOI":"10.1145\/3526241.3530335","type":"proceedings-article","created":{"date-parts":[[2022,6,2]],"date-time":"2022-06-02T14:37:09Z","timestamp":1654180629000},"page":"205-210","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["RACE: A Reinforcement Learning Framework for Improved Adaptive Control of NoC Channel Buffers"],"prefix":"10.1145","author":[{"given":"Kamil","family":"Khan","sequence":"first","affiliation":[{"name":"Colorado State University, Fort Collins, CO, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudeep","family":"Pasricha","sequence":"additional","affiliation":[{"name":"Colorado State University, Fort Collins, CO, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryan Gary","family":"Kim","sequence":"additional","affiliation":[{"name":"Colorado State University, Fort Collins, CO, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,6,6]]},"reference":[{"key":"e_1_3_2_2_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"e_1_3_2_2_2_1","first-page":"25","volume-title":"Inter. Symp. on Comp. Arch.","author":"Daya B. K.","year":"2014","unstructured":"B. K. Daya : A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering,\" in Proc . Inter. Symp. on Comp. Arch. , Jun. 2014 , pp. 25 -- 36 . B. K. Daya et al., \"SCORPIO: A 36-core research chip demonstrating snoopy coherence on a scalable mesh NoC with in-network ordering,\" in Proc. Inter. Symp. on Comp. Arch., Jun. 2014, pp. 25--36."},{"key":"e_1_3_2_2_3_1","unstructured":"P. Kundu \"On-die interconnects for next generation CMPS \" presented at The Workshop on On- and Off-Chip Interconnection Networks for Multicore Syst. Stanford CA USA Dec. 6--7 2006  P. Kundu \"On-die interconnects for next generation CMPS \" presented at The Workshop on On- and Off-Chip Interconnection Networks for Multicore Syst. Stanford CA USA Dec. 6--7 2006"},{"key":"e_1_3_2_2_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382142"},{"key":"e_1_3_2_2_5_1","first-page":"196","volume-title":"Int. Symp. on Comp. Architecture","author":"Moscibroda T.","year":"2009","unstructured":"T. Moscibroda and O. Mutlu , \" A case for bufferless routing in on-chip networks,\" in Proc . Int. Symp. on Comp. Architecture , Jun. 2009 , pp. 196 -- 207 . T. Moscibroda and O. Mutlu, \"A case for bufferless routing in on-chip networks,\" in Proc. Int. Symp. on Comp. Architecture, Jun. 2009, pp. 196--207."},{"key":"e_1_3_2_2_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835942"},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.2986297"},{"key":"e_1_3_2_2_8_1","volume-title":"Surv.","volume":"38","author":"Bjerregaard T.","unstructured":"T. Bjerregaard and S. Mahadevan , \" A survey of research and practices of Network-on-chip,\" ACM Comput . Surv. , vol. 38 , no. 1, Jun. 2006, p. 1 T. Bjerregaard and S. Mahadevan, \"A survey of research and practices of Network-on-chip,\" ACM Comput. Surv., vol. 38, no. 1, Jun. 2006, p. 1"},{"key":"e_1_3_2_2_9_1","first-page":"132","volume-title":"IEEE\/ACM Int. Symp. on Networks-on-Chip","author":"Hesse R.","year":"2012","unstructured":"R. Hesse , J. Nicholls , and N. E. Jerger , \" Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels,\" in Proc . IEEE\/ACM Int. Symp. on Networks-on-Chip , May 2012 , pp. 132 -- 141 . R. Hesse, J. Nicholls, and N. E. Jerger, \"Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels,\" in Proc. IEEE\/ACM Int. Symp. on Networks-on-Chip, May 2012, pp. 132--141."},{"key":"e_1_3_2_2_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2401013"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322274"},{"key":"e_1_3_2_2_12_1","volume-title":"arXiv","author":"Li Y.","year":"1810","unstructured":"Y. Li , \"Deep Reinforcement Learning,\", 2018 , arXiv : 1810 .06339. Y. Li, \"Deep Reinforcement Learning,\", 2018, arXiv:1810.06339."},{"key":"e_1_3_2_2_13_1","volume-title":"Playing Atari with Deep Reinforcement Learn","author":"Mnih V.","year":"2013","unstructured":"V. Mnih , \" Playing Atari with Deep Reinforcement Learn .,\" 2013 , arXiv: 1312.5602 V. Mnih et al., \"Playing Atari with Deep Reinforcement Learn.,\" 2013, arXiv: 1312.5602"},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF00992698"},{"key":"e_1_3_2_2_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2015.7245728"},{"key":"e_1_3_2_2_16_1","volume-title":"Dept. of Comp. Sci.","author":"Bienia C.","year":"2011","unstructured":"C. Bienia , \"Benchmarking Modern Multiprocessors,\" Ph. D. dissertation , Dept. of Comp. Sci. , Princeton University , NJ , Jan. 2011 , p. 153. C. Bienia, \"Benchmarking Modern Multiprocessors,\" Ph.D. dissertation, Dept. of Comp. Sci., Princeton University, NJ, Jan. 2011, p. 153."},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.5555\/2821589"},{"key":"e_1_3_2_2_18_1","volume-title":"On-Chip Communication Architectures","author":"Pasricha S.","year":"2008","unstructured":"S. Pasricha , and N. Dutt , \" On-Chip Communication Architectures \", Burlington, NJ, USA : Morgan Kauffman , 2008 . S. Pasricha, and N. Dutt, \"On-Chip Communication Architectures\", Burlington, NJ, USA: Morgan Kauffman, 2008."}],"event":{"name":"GLSVLSI '22: Great Lakes Symposium on VLSI 2022","location":"Irvine CA USA","acronym":"GLSVLSI '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2022"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530335","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3526241.3530335","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:16Z","timestamp":1750186936000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530335"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,6]]},"references-count":18,"alternative-id":["10.1145\/3526241.3530335","10.1145\/3526241"],"URL":"https:\/\/doi.org\/10.1145\/3526241.3530335","relation":{},"subject":[],"published":{"date-parts":[[2022,6,6]]},"assertion":[{"value":"2022-06-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}