{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,21]],"date-time":"2026-07-21T14:23:28Z","timestamp":1784643808654,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T00:00:00Z","timestamp":1654473600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"BMBF","award":["01IW1900"],"award-info":[{"award-number":["01IW1900"]}]},{"name":"BMBF","award":["16ME0127"],"award-info":[{"award-number":["16ME0127"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,6]]},"DOI":"10.1145\/3526241.3530340","type":"proceedings-article","created":{"date-parts":[[2022,6,2]],"date-time":"2022-06-02T14:37:09Z","timestamp":1654180629000},"page":"97-103","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing"],"prefix":"10.1145","author":[{"given":"Niklas","family":"Bruns","sequence":"first","affiliation":[{"name":"University of Bremen, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vladimir","family":"Herdt","sequence":"additional","affiliation":[{"name":"University of Bremen &amp; DFKI GmbH, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniel","family":"Gro\u00dfe","sequence":"additional","affiliation":[{"name":"Johannes Kepler University &amp; DFKI GmbH, Linz, Austria"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[{"name":"University of Bremen &amp; DFKI GmbH, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,6,6]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2012. RISC-V Torture Test Generator. https:\/\/github.com\/ucb-bar\/riscv-torture.  2012. RISC-V Torture Test Generator. https:\/\/github.com\/ucb-bar\/riscv-torture."},{"key":"e_1_3_2_1_2_1","unstructured":"2013. RISC-V ISA Tests. https:\/\/github.com\/riscv\/riscv-tests.  2013. RISC-V ISA Tests. https:\/\/github.com\/riscv\/riscv-tests."},{"key":"e_1_3_2_1_3_1","unstructured":"2016. Fuzz testing in Chromium. https:\/\/chromium.googlesource.com\/chromium\/src\/+\/master\/testing\/libfuzzer\/README.md  2016. Fuzz testing in Chromium. https:\/\/chromium.googlesource.com\/chromium\/src\/+\/master\/testing\/libfuzzer\/README.md"},{"key":"e_1_3_2_1_4_1","unstructured":"2016. SpinalHDL. https:\/\/github.com\/SpinalHDL\/SpinalHDL  2016. SpinalHDL. https:\/\/github.com\/SpinalHDL\/SpinalHDL"},{"key":"e_1_3_2_1_5_1","unstructured":"2018. AFL: Understanding the status screen. https:\/\/github.com\/google\/AFL\/blob\/fab1ca5ed7e3552833a18fc2116d33a9241699bc\/docs\/status_screen.txt.  2018. AFL: Understanding the status screen. https:\/\/github.com\/google\/AFL\/blob\/fab1ca5ed7e3552833a18fc2116d33a9241699bc\/docs\/status_screen.txt."},{"key":"e_1_3_2_1_6_1","unstructured":"2018. american fuzzy lop. http:\/\/lcamtuf.coredump.cx\/afl\/.  2018. american fuzzy lop. http:\/\/lcamtuf.coredump.cx\/afl\/."},{"key":"e_1_3_2_1_7_1","unstructured":"2018. libFuzzer - a library for coverage-guided fuzz testing. https:\/\/llvm.org\/docs\/LibFuzzer.html.  2018. libFuzzer - a library for coverage-guided fuzz testing. https:\/\/llvm.org\/docs\/LibFuzzer.html."},{"key":"e_1_3_2_1_8_1","unstructured":"2018. Microsoft security development lifecycle. https:\/\/www.microsoft.com\/en-us\/sdl\/process\/verification.aspx.  2018. Microsoft security development lifecycle. https:\/\/www.microsoft.com\/en-us\/sdl\/process\/verification.aspx."},{"key":"e_1_3_2_1_9_1","unstructured":"2018. OSS-Fuzz - Continuous Fuzzing for Open Source Software. https:\/\/github.com\/google\/oss-fuzz.  2018. OSS-Fuzz - Continuous Fuzzing for Open Source Software. https:\/\/github.com\/google\/oss-fuzz."},{"key":"e_1_3_2_1_10_1","unstructured":"2020. About RISC-V. https:\/\/riscv.org\/about\/  2020. About RISC-V. https:\/\/riscv.org\/about\/"},{"key":"e_1_3_2_1_11_1","unstructured":"2020. OneSpin 360 DV RISC-V Verification App. https:\/\/www.onespin.com\/solutions\/risc-v.  2020. OneSpin 360 DV RISC-V Verification App. https:\/\/www.onespin.com\/solutions\/risc-v."},{"key":"e_1_3_2_1_12_1","unstructured":"2020. RISC-V Compliance Task Group. https:\/\/github.com\/riscv\/riscv-compliance.  2020. RISC-V Compliance Task Group. https:\/\/github.com\/riscv\/riscv-compliance."},{"key":"e_1_3_2_1_13_1","unstructured":"2020. RISC-V Formal Verification Framework. https:\/\/github.com\/SymbioticEDA\/riscv-formal.  2020. RISC-V Formal Verification Framework. https:\/\/github.com\/SymbioticEDA\/riscv-formal."},{"key":"e_1_3_2_1_14_1","unstructured":"2020. RISCV-DV. https:\/\/github.com\/google\/riscv-dv.  2020. RISCV-DV. https:\/\/github.com\/google\/riscv-dv."},{"key":"e_1_3_2_1_15_1","unstructured":"2020. VexRiscv. https:\/\/github.com\/SpinalHDL\/VexRiscv Commit: 98de02051e1a5c9400c022dc61acd4bd0507f8a5.  2020. VexRiscv. https:\/\/github.com\/SpinalHDL\/VexRiscv Commit: 98de02051e1a5c9400c022dc61acd4bd0507f8a5."},{"key":"e_1_3_2_1_16_1","unstructured":"2021. verilator. https:\/\/www.veripool.org\/verilator\/.  2021. verilator. https:\/\/www.veripool.org\/verilator\/."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"A. Adir E. Almog L. Fournier E. Marcus M. Rimon M. Vinov and A. Ziv. 2004. Genesys-Pro: innovations in test program generation for functional processor verification. IEEE Design & Test of Comp. (2004) 84--93.  A. Adir E. Almog L. Fournier E. Marcus M. Rimon M. Vinov and A. Ziv. 2004. Genesys-Pro: innovations in test program generation for functional processor verification. IEEE Design & Test of Comp. (2004) 84--93.","DOI":"10.1109\/MDT.2004.1277900"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2021.3077368"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"Niklas Bruns Vladimir Herdt Eyck Jentzsch and Rolf Drechsler. 2022. Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging. In Design Automation and Test in Europe.  Niklas Bruns Vladimir Herdt Eyck Jentzsch and Rolf Drechsler. 2022. Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging. In Design Automation and Test in Europe.","DOI":"10.23919\/DATE54114.2022.9774771"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"crossref","unstructured":"Brian Campbell and Ian Stark. 2014. Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation. In Formal Methods for Industrial Critical Systems Fr\u00e9d\u00e9ric Lang and Francesco Flammini (Eds.). 185--199.  Brian Campbell and Ian Stark. 2014. Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation. In Formal Methods for Industrial Critical Systems Fr\u00e9d\u00e9ric Lang and Francesco Flammini (Eds.). 185--199.","DOI":"10.1007\/978-3-319-10702-8_13"},{"key":"e_1_3_2_1_21_1","volume-title":"IEEE International High Level Design Validation and Test Workshop. 145--150","author":"Emek R.","unstructured":"R. Emek , I. Jaeger , Y. Naveh , G. Bergman , G. Aloni , Y. Katz , M. Farkash , I. Dozoretz , and A. Goldin . 2002. X-Gen: a random test-case generator for systems and SoCs . In IEEE International High Level Design Validation and Test Workshop. 145--150 . R. Emek, I. Jaeger, Y. Naveh, G. Bergman, G. Aloni, Y. Katz, M. Farkash, I. Dozoretz, and A. Goldin. 2002. X-Gen: a random test-case generator for systems and SoCs. In IEEE International High Level Design Validation and Test Workshop. 145--150."},{"key":"e_1_3_2_1_22_1","volume-title":"Design Automation Conf. 286--291","author":"Fine S.","unstructured":"S. Fine and A. Ziv . 2003. Coverage directed test generation for functional verification using Bayesian networks . In Design Automation Conf. 286--291 . S. Fine and A. Ziv. 2003. Coverage directed test generation for functional verification using Bayesian networks. In Design Automation Conf. 286--291."},{"key":"e_1_3_2_1_23_1","volume-title":"Hardware and Software: Verification and Testing","author":"Fournier Laurent","unstructured":"Laurent Fournier and Avi Ziv . 2008. Using Virtual Coverage to Hit Hard-To- Reach Events . In Hardware and Software: Verification and Testing . Springer Berlin Heidelberg , 104--119. Laurent Fournier and Avi Ziv. 2008. Using Virtual Coverage to Hit Hard-To- Reach Events. In Hardware and Software: Verification and Testing. Springer Berlin Heidelberg, 104--119."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe and Rolf Drechsler. 2020. Towards Specification and Testing of RISC-V ISA Compliance. In Design Automation and Test in Europe. 995--998.  Vladimir Herdt Daniel Gro\u00dfe and Rolf Drechsler. 2020. Towards Specification and Testing of RISC-V ISA Compliance. In Design Automation and Test in Europe. 995--998.","DOI":"10.23919\/DATE48585.2020.9116193"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2018. Extensible and Configurable RISC-V based Virtual Prototype. In Forum on Specification and Design Languages.  Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2018. Extensible and Configurable RISC-V based Virtual Prototype. In Forum on Specification and Design Languages.","DOI":"10.1109\/FDL.2018.8524047"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2019. Verifying Instruction Set Simulators using Coverage-guided Fuzzing. In Design Automation and Test in Europe.  Vladimir Herdt Daniel Gro\u00dfe Hoang M. Le and Rolf Drechsler. 2019. Verifying Instruction Set Simulators using Coverage-guided Fuzzing. In Design Automation and Test in Europe.","DOI":"10.23919\/DATE.2019.8714912"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"Vladimir Herdt Daniel Gro\u00dfe Eyck Jentzsch and Rolf Drechsler. 2020. Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. In Forum on Specification and Design Languages. 1--7.  Vladimir Herdt Daniel Gro\u00dfe Eyck Jentzsch and Rolf Drechsler. 2020. Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. In Forum on Specification and Design Languages. 1--7.","DOI":"10.1109\/FDL50818.2020.9232941"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","unstructured":"Charalambos Ioannides Geoff Barrett and Kerstin Eder. 2011. Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation. In Hardware and Software: Verification and Testing Sharon Barner Ian Harris Daniel Kroening and Orna Raz (Eds.).  Charalambos Ioannides Geoff Barrett and Kerstin Eder. 2011. Feedback-Based Coverage Directed Test Generation: An Industrial Evaluation. In Hardware and Software: Verification and Testing Sharon Barner Ian Harris Daniel Kroening and Orna Raz (Eds.).","DOI":"10.1007\/978-3-642-19583-9_13"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"crossref","unstructured":"Y. Katz M. Rimon and A. Ziv. 2012. Generating instruction streams using abstract CSP. In Design Automation and Test in Europe. 15--20.  Y. Katz M. Rimon and A. Ziv. 2012. Generating instruction streams using abstract CSP. In Design Automation and Test in Europe. 15--20.","DOI":"10.1109\/DATE.2012.6176425"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3243734.3243804"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240842"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"crossref","unstructured":"Weiqin Ma A. Forin and Jyh-Charn Liu. 2010. Rapid prototyping and compact testing of CPU emulators. In RSP. 1--7.  Weiqin Ma A. Forin and Jyh-Charn Liu. 2010. Rapid prototyping and compact testing of CPU emulators. In RSP. 1--7.","DOI":"10.1109\/RSP.2010.5656339"},{"key":"e_1_3_2_1_33_1","volume-title":"Giampaolo Fresi Roglia, and Danilo Bruschi","author":"Martignoni Lorenzo","year":"2009","unstructured":"Lorenzo Martignoni , Roberto Paleari , Giampaolo Fresi Roglia, and Danilo Bruschi . 2009 . Testing CPU Emulators. In ISSTA. 261--272. Lorenzo Martignoni, Roberto Paleari, Giampaolo Fresi Roglia, and Danilo Bruschi. 2009. Testing CPU Emulators. In ISSTA. 261--272."},{"key":"e_1_3_2_1_34_1","volume-title":"An Empirical Study of the Reliability of UNIX Utilities. Commun. ACM","author":"Miller Barton P.","year":"1990","unstructured":"Barton P. Miller , Louis Fredriksen , and Bryan So. 1990. An Empirical Study of the Reliability of UNIX Utilities. Commun. ACM ( 1990 ), 32--44. Barton P. Miller, Louis Fredriksen, and Bryan So. 1990. An Empirical Study of the Reliability of UNIX Utilities. Commun. ACM (1990), 32--44."},{"key":"e_1_3_2_1_35_1","volume-title":"SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. In European Test Symposium.","author":"Ruep Katharina","year":"2022","unstructured":"Katharina Ruep and Daniel Gro\u00dfe . 2022 . SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. In European Test Symposium. Katharina Ruep and Daniel Gro\u00dfe. 2022. SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs. In European Test Symposium."},{"key":"e_1_3_2_1_36_1","volume-title":"Fuzzing Hardware Like Software. CoRR abs\/2102.02308","author":"Trippel Timothy","year":"2021","unstructured":"Timothy Trippel , Kang G. Shin , Alex Chernyakhovsky , Garret Kelly , Dominic Rizzo , and Matthew Hicks . 2021. Fuzzing Hardware Like Software. CoRR abs\/2102.02308 ( 2021 ). arXiv:2102.02308 https:\/\/arxiv.org\/abs\/2102.02308 Timothy Trippel, Kang G. Shin, Alex Chernyakhovsky, Garret Kelly, Dominic Rizzo, and Matthew Hicks. 2021. Fuzzing Hardware Like Software. CoRR abs\/2102.02308 (2021). arXiv:2102.02308 https:\/\/arxiv.org\/abs\/2102.02308"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"crossref","unstructured":"Harry Wagstaff Tom Spink and Bj\u00f6rn Franke. 2014. Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators. In CASES. 1--10.  Harry Wagstaff Tom Spink and Bj\u00f6rn Franke. 2014. Automated ISA branch coverage analysis and test case generation for retargetable instruction set simulators. In CASES. 1--10.","DOI":"10.1145\/2656106.2656113"},{"key":"e_1_3_2_1_38_1","unstructured":"Andrew Waterman and Krste Asanovic (Eds.). 2019. The RISC-V Instruction Set Manual; Volume I: Unprivileged ISA. RISC-V Foundation.  Andrew Waterman and Krste Asanovic (Eds.). 2019. The RISC-V Instruction Set Manual; Volume I: Unprivileged ISA. RISC-V Foundation."},{"key":"e_1_3_2_1_39_1","volume-title":"Volume II: Privileged Architecture","author":"Waterman Andrew","year":"2019","unstructured":"Andrew Waterman and Krste Asanovic (Eds.). 2019 . The RISC-V Instruction Set Manual ; Volume II: Privileged Architecture . RISC-V Foundation . Andrew Waterman and Krste Asanovic (Eds.). 2019. The RISC-V Instruction Set Manual; Volume II: Privileged Architecture. RISC-V Foundation."}],"event":{"name":"GLSVLSI '22: Great Lakes Symposium on VLSI 2022","location":"Irvine CA USA","acronym":"GLSVLSI '22","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2022"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530340","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3526241.3530340","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:16Z","timestamp":1750186936000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530340"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,6]]},"references-count":39,"alternative-id":["10.1145\/3526241.3530340","10.1145\/3526241"],"URL":"https:\/\/doi.org\/10.1145\/3526241.3530340","relation":{},"subject":[],"published":{"date-parts":[[2022,6,6]]},"assertion":[{"value":"2022-06-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}