{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:40:07Z","timestamp":1750189207304,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":17,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T00:00:00Z","timestamp":1654473600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,6]]},"DOI":"10.1145\/3526241.3530362","type":"proceedings-article","created":{"date-parts":[[2022,6,2]],"date-time":"2022-06-02T14:37:09Z","timestamp":1654180629000},"page":"123-126","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking"],"prefix":"10.1145","author":[{"given":"Gagan","family":"Gayari","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Guwahati, Guwahati, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chandan","family":"Karfa","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Guwahati, Indian Institute of Technology, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Prithwijit","family":"Guha","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Guwahati, Guwahati, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,6,6]]},"reference":[{"key":"e_1_3_2_2_1_1","volume-title":"Fastsim: A fast simulation framework for high-level synthesis","author":"Abderehman M.","year":"2021","unstructured":"Abderehman , M. , Patidar , J. , Oza , J. , Nigam , Y. , Khader , T. A. , and Karfa , C . Fastsim: A fast simulation framework for high-level synthesis . IEEE TCAD ( 2021 ), 1--1. Abderehman, M., Patidar, J., Oza, J., Nigam, Y., Khader, T. A., and Karfa, C. Fastsim: A fast simulation framework for high-level synthesis. IEEE TCAD (2021), 1--1."},{"key":"e_1_3_2_2_2_1","first-page":"1118","volume-title":"DATE","author":"Badier H.","year":"2019","unstructured":"Badier , H. , Lann , J.-C. L. , Coussy , P. , and Gogniat , G . Transient key-based obfuscation for hls in an untrusted cloud environment . In DATE ( 2019 ), pp. 1118 -- 1123 . Badier, H., Lann, J.-C. L., Coussy, P., and Gogniat, G. Transient key-based obfuscation for hls in an untrusted cloud environment. In DATE (2019), pp. 1118--1123."},{"key":"e_1_3_2_2_3_1","first-page":"1","article-title":"Preventing ic piracy using reconfigurable logic barriers","volume":"27","author":"Baumgarten A.","year":"2010","unstructured":"Baumgarten , A. , Tyagi , A. , and Zambreno , J . Preventing ic piracy using reconfigurable logic barriers . IEEE D&T of Computers 27 , 1 ( 2010 ), 66--75. Baumgarten, A., Tyagi, A., and Zambreno, J. Preventing ic piracy using reconfigurable logic barriers. IEEE D&T of Computers 27, 1 (2010), 66--75.","journal-title":"IEEE D&T of Computers"},{"key":"e_1_3_2_2_4_1","first-page":"3828","article-title":"Sail: Analyzing structural artifacts of logic locking using machine learning","volume":"16","author":"Chakraborty P.","year":"2021","unstructured":"Chakraborty , P. , Cruz , J. , Alaql , A. , and Bhunia , S . Sail: Analyzing structural artifacts of logic locking using machine learning . IEEE TIFS 16 ( 2021 ), 3828 -- 3842 . Chakraborty, P., Cruz, J., Alaql, A., and Bhunia, S. Sail: Analyzing structural artifacts of logic locking using machine learning. IEEE TIFS 16 (2021), 3828--3842.","journal-title":"IEEE TIFS"},{"key":"e_1_3_2_2_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942134"},{"key":"e_1_3_2_2_6_1","volume-title":"30th USENIX Security Symposium (USENIX Security 21)","author":"Han Z.","year":"2021","unstructured":"Han , Z. , Yasin , M. , and Rajendran , J. J . Does logic locking work with EDA tools? In 30th USENIX Security Symposium (USENIX Security 21) ( 2021 ). Han, Z., Yasin, M., and Rajendran, J. J. Does logic locking work with EDA tools? In 30th USENIX Security Symposium (USENIX Security 21) (2021)."},{"key":"e_1_3_2_2_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST51057.2020.9358261"},{"key":"e_1_3_2_2_8_1","first-page":"550","volume-title":"DATE","author":"Karfa C.","year":"2020","unstructured":"Karfa , C. , Chouksey , R. , Pilato , C. , Garg , S. , and Karri , R . Is register transfer level locking secure ? In DATE ( 2020 ), pp. 550 -- 555 . Karfa, C., Chouksey, R., Pilato, C., Garg, S., and Karri, R. Is register transfer level locking secure? In DATE (2020), pp. 550--555."},{"key":"e_1_3_2_2_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2019.8697421"},{"key":"e_1_3_2_2_10_1","first-page":"7","article-title":"Assure: Rtl locking against an untrusted foundry","volume":"29","author":"Pilato C.","year":"2021","unstructured":"Pilato , C. , Chowdhury , A. B. , Sciuto , D. , Garg , S. , and Karri , R . Assure: Rtl locking against an untrusted foundry . IEEE TVLSI 29 , 7 ( 2021 ), 1306--1318. Pilato, C., Chowdhury, A. B., Sciuto, D., Garg, S., and Karri, R. Assure: Rtl locking against an untrusted foundry. IEEE TVLSI 29, 7 (2021), 1306--1318.","journal-title":"IEEE TVLSI"},{"key":"e_1_3_2_2_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196126"},{"key":"e_1_3_2_2_12_1","first-page":"11","article-title":"Belling the cad: Toward security-centric electronic system design","volume":"34","author":"Rajendran J.","year":"2015","unstructured":"Rajendran , J. , Ali , A. , Sinanoglu , O. , and Karri , R . Belling the cad: Toward security-centric electronic system design . IEEE TCAD 34 , 11 ( 2015 ), 1756--1769. Rajendran, J., Ali, A., Sinanoglu, O., and Karri, R. Belling the cad: Toward security-centric electronic system design. IEEE TCAD 34, 11 (2015), 1756--1769.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_2_13_1","first-page":"936","volume-title":"DATE","author":"Sirone D.","year":"2019","unstructured":"Sirone , D. , and Subramanyan , P . Functional analysis attacks on logic locking . In DATE ( 2019 ), pp. 936 -- 939 . Sirone, D., and Subramanyan, P. Functional analysis attacks on logic locking. In DATE (2019), pp. 936--939."},{"key":"e_1_3_2_2_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"e_1_3_2_2_15_1","volume-title":"Anti-sat: Mitigating sat attack on logic locking","author":"Xie Y.","year":"2018","unstructured":"Xie , Y. , and Srivastava , A . Anti-sat: Mitigating sat attack on logic locking . IEEE TCAD ( 2018 ), 199--207. Xie, Y., and Srivastava, A. Anti-sat: Mitigating sat attack on logic locking. IEEE TCAD (2018), 199--207."},{"key":"e_1_3_2_2_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"e_1_3_2_2_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"}],"event":{"name":"GLSVLSI '22: Great Lakes Symposium on VLSI 2022","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Irvine CA USA","acronym":"GLSVLSI '22"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2022"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530362","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3526241.3530362","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:16Z","timestamp":1750186936000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530362"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,6]]},"references-count":17,"alternative-id":["10.1145\/3526241.3530362","10.1145\/3526241"],"URL":"https:\/\/doi.org\/10.1145\/3526241.3530362","relation":{},"subject":[],"published":{"date-parts":[[2022,6,6]]},"assertion":[{"value":"2022-06-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}