{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:16:22Z","timestamp":1750220182443,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":21,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T00:00:00Z","timestamp":1654473600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,6]]},"DOI":"10.1145\/3526241.3530380","type":"proceedings-article","created":{"date-parts":[[2022,6,2]],"date-time":"2022-06-02T14:37:09Z","timestamp":1654180629000},"page":"379-382","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["MOCCA: A Process Variation Tolerant Systolic DNN Accelerator using CNFETs in Monolithic 3D"],"prefix":"10.1145","author":[{"given":"Samuel J.","family":"Engers","sequence":"first","affiliation":[{"name":"Indiana University Bloomington, Bloomington, IN, USA"}]},{"given":"Cheng","family":"Chu","sequence":"additional","affiliation":[{"name":"Indiana University Bloomington, Bloomington, IN, USA"}]},{"given":"Dawen","family":"Xu","sequence":"additional","affiliation":[{"name":"Seehi Microelectronics Co., Ltd, Beijin, China"}]},{"given":"Ying","family":"Wang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences, Beijing, China"}]},{"given":"Fan","family":"Chen","sequence":"additional","affiliation":[{"name":"Indiana University Bloomington, Bloomington, IN, USA"}]}],"member":"320","published-online":{"date-parts":[[2022,6,6]]},"reference":[{"key":"e_1_3_2_2_1_1","volume-title":"In-Datacenter Performance Analysis of a Tensor Processing Unit,\" in ISCA","author":"Jouppi N. P.","year":"2017","unstructured":"N. P. Jouppi , \" In-Datacenter Performance Analysis of a Tensor Processing Unit,\" in ISCA , 2017 . N. P. Jouppi et al., \"In-Datacenter Performance Analysis of a Tensor Processing Unit,\" in ISCA, 2017."},{"key":"e_1_3_2_2_2_1","doi-asserted-by":"crossref","unstructured":"D. Woods \"Photonic Neural Networks \" in Nature Physics 2012.  D. Woods \"Photonic Neural Networks \" in Nature Physics 2012.","DOI":"10.1038\/nphys2283"},{"key":"e_1_3_2_2_3_1","volume-title":"A compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part II: Full Device Model and Circuit Performance Benchmarking,\" IEEE T-ED","author":"Deng J.","year":"2007","unstructured":"J. Deng , \" A compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part II: Full Device Model and Circuit Performance Benchmarking,\" IEEE T-ED , 2007 . J. Deng et al., \"A compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application-Part II: Full Device Model and Circuit Performance Benchmarking,\" IEEE T-ED, 2007."},{"key":"e_1_3_2_2_4_1","volume-title":"Sub-10 nm Carbon Nanotube Transistor,\" Nano letters","author":"Franklin A. D.","year":"2012","unstructured":"A. D. Franklin , \" Sub-10 nm Carbon Nanotube Transistor,\" Nano letters , 2012 . A. D. Franklin et al., \"Sub-10 nm Carbon Nanotube Transistor,\" Nano letters, 2012."},{"key":"e_1_3_2_2_5_1","volume":"200","author":"Yu C.","unstructured":"C. Yu , \"Thermal Conductance and Thermopower of an Individual Single- Wall Carbon Nanotube,\" Nano Letters , 200 5. C. Yu et al., \"Thermal Conductance and Thermopower of an Individual Single- Wall Carbon Nanotube,\" Nano Letters, 2005.","journal-title":"\"Thermal Conductance and Thermopower of an Individual Single- Wall Carbon Nanotube,\" Nano Letters"},{"key":"e_1_3_2_2_6_1","volume-title":"Resistive RAM, and Silicon FETs,\" in IEDM","author":"Shulaker M. M.","year":"2014","unstructured":"M. M. Shulaker , \" Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs , Resistive RAM, and Silicon FETs,\" in IEDM , 2014 . M. M. Shulaker et al., \"Monolithic 3D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs,\" in IEDM, 2014."},{"key":"e_1_3_2_2_7_1","volume-title":"Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs,\" IEEE TVLSIS","author":"Banerjee S.","year":"2020","unstructured":"S. Banerjee , \" Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs,\" IEEE TVLSIS , 2020 . S. Banerjee et al., \"Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs,\" IEEE TVLSIS, 2020."},{"key":"e_1_3_2_2_8_1","volume-title":"Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations,\" in DAC","author":"Zhang J.","year":"2009","unstructured":"J. Zhang , \" Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations,\" in DAC , 2009 . J. Zhang et al., \"Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations,\" in DAC, 2009."},{"key":"e_1_3_2_2_9_1","volume-title":"Probabilistic Analysis and Design of Metallic-Carbon-Nanotube- Tolerant Digital Logic Circuits,\" TCAD","author":"Zhang J.","year":"2009","unstructured":"J. Zhang , \" Probabilistic Analysis and Design of Metallic-Carbon-Nanotube- Tolerant Digital Logic Circuits,\" TCAD , 2009 . J. Zhang et al., \"Probabilistic Analysis and Design of Metallic-Carbon-Nanotube- Tolerant Digital Logic Circuits,\" TCAD, 2009."},{"key":"e_1_3_2_2_10_1","volume-title":"Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction,\" Science","author":"Zhang G.","year":"2006","unstructured":"G. Zhang , \" Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction,\" Science , 2006 . G. Zhang et al., \"Selective Etching of Metallic Carbon Nanotubes by Gas-Phase Reaction,\" Science, 2006."},{"key":"e_1_3_2_2_11_1","volume-title":"The N3XT Approach to Energy-Efficient Abundant-Data Computing,\" in Proceedings of the IEEE","author":"Aly M. M. S.","year":"2018","unstructured":"M. M. S. Aly , \" The N3XT Approach to Energy-Efficient Abundant-Data Computing,\" in Proceedings of the IEEE , 2018 . M. M. S. Aly et al., \"The N3XT Approach to Energy-Efficient Abundant-Data Computing,\" in Proceedings of the IEEE, 2018."},{"key":"e_1_3_2_2_12_1","volume-title":"Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D,\" in DATE","author":"Chen F.","year":"2021","unstructured":"F. Chen , \" Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D,\" in DATE , 2021 . F. Chen et al., \"Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D,\" in DATE, 2021."},{"key":"e_1_3_2_2_13_1","volume-title":"Semicond. Manuf.","author":"Sarangi S.","year":"2008","unstructured":"S. Sarangi : A Model of Process Variation and Resulting Timing Errors for Microarchitects,\" in IEEE Trans . Semicond. Manuf. , 2008 . S. Sarangi et al., \"VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects,\" in IEEE Trans. Semicond. Manuf., 2008."},{"key":"e_1_3_2_2_14_1","volume-title":"Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,\" in DAC","author":"Zhang J.","year":"2008","unstructured":"J. Zhang , \" Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,\" in DAC , 2008 . J. Zhang et al., \"Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,\" in DAC, 2008."},{"key":"e_1_3_2_2_15_1","unstructured":"G. Hills \"Variation-Aware Nanosystem Design Kit (NDK) \" 2015.  G. Hills \"Variation-Aware Nanosystem Design Kit (NDK) \" 2015."},{"key":"e_1_3_2_2_16_1","volume-title":"Lee et al., \"A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime-Part I: Intrinsic Elements,\" T-ED","author":"C.","year":"2015","unstructured":"C. . Lee et al., \"A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime-Part I: Intrinsic Elements,\" T-ED , 2015 . C. . Lee et al., \"A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime-Part I: Intrinsic Elements,\" T-ED, 2015."},{"key":"e_1_3_2_2_17_1","volume-title":"CNFET-based High Throughput Register File Architecture,\" in ICCD","author":"Li T.","year":"2016","unstructured":"T. Li , \" CNFET-based High Throughput Register File Architecture,\" in ICCD , 2016 . T. Li et al., \"CNFET-based High Throughput Register File Architecture,\" in ICCD, 2016."},{"key":"e_1_3_2_2_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196132"},{"key":"e_1_3_2_2_19_1","volume-title":"SCALE-Sim: Systolic CNN Accelerator Simulator,\" arXiv e-prints","author":"Samajdar A.","year":"2018","unstructured":"A. Samajdar , \" SCALE-Sim: Systolic CNN Accelerator Simulator,\" arXiv e-prints , 2018 . A. Samajdar et al., \"SCALE-Sim: Systolic CNN Accelerator Simulator,\" arXiv e-prints, 2018."},{"key":"e_1_3_2_2_20_1","volume-title":"Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding,\" in ICLR","author":"Han S.","year":"2016","unstructured":"S. Han , \" Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding,\" in ICLR , 2016 . S. Han et al., \"Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding,\" in ICLR, 2016."},{"key":"e_1_3_2_2_21_1","volume-title":"A 14nm FinFET Transistor-Level 3D Partitioning Design to Enable High-Performance and Low-Cost Monolithic 3D IC,\" in IEDM","author":"Shi J.","year":"2016","unstructured":"J. Shi , \" A 14nm FinFET Transistor-Level 3D Partitioning Design to Enable High-Performance and Low-Cost Monolithic 3D IC,\" in IEDM , 2016 . J. Shi et al., \"A 14nm FinFET Transistor-Level 3D Partitioning Design to Enable High-Performance and Low-Cost Monolithic 3D IC,\" in IEDM, 2016."}],"event":{"name":"GLSVLSI '22: Great Lakes Symposium on VLSI 2022","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Irvine CA USA","acronym":"GLSVLSI '22"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2022"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530380","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3526241.3530380","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:17Z","timestamp":1750186937000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3526241.3530380"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,6]]},"references-count":21,"alternative-id":["10.1145\/3526241.3530380","10.1145\/3526241"],"URL":"https:\/\/doi.org\/10.1145\/3526241.3530380","relation":{},"subject":[],"published":{"date-parts":[[2022,6,6]]},"assertion":[{"value":"2022-06-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}