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Syst."],"published-print":{"date-parts":[[2023,3,31]]},"abstract":"<jats:p>\n            In this work, we present a\n            <jats:italic>C<\/jats:italic>\n            ompiler-integrated,\n            <jats:italic>E<\/jats:italic>\n            xtensible\n            <jats:italic>D<\/jats:italic>\n            omain Specific System on Chip\n            <jats:italic>R<\/jats:italic>\n            untime (CEDR) ecosystem to facilitate research toward addressing the challenges of architecture, system software, and application development with distinct plug-and-play integration points in a unified compile time and runtime workflow. We demonstrate the utility of CEDR on the Xilinx Zynq MPSoC-ZCU102 for evaluating performance of pre-silicon hardware in the trade space of SoC configuration, scheduling policy and workload complexity based on dynamically arriving workload scenarios composed of real-life signal processing applications scaling to thousands of application instances with Fast Fourier Transform and matrix multiply accelerators. We provide insights into the tradeoffs present in this design space through a number of distinct case studies. CEDR is portable and has been deployed and validated on Odroid-XU3, X86, and Nvidia Jetson Xavier-based SoC platforms. Taken together, CEDR is a capable environment for enabling research in exploring the boundaries of productive application development, resource management heuristic development, and hardware configuration analysis for heterogeneous architectures.\n          <\/jats:p>","DOI":"10.1145\/3529257","type":"journal-article","created":{"date-parts":[[2022,4,13]],"date-time":"2022-04-13T11:53:39Z","timestamp":1649850819000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":22,"title":["CEDR: A Compiler-integrated, Extensible DSSoC Runtime"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1066-5578","authenticated-orcid":false,"given":"Joshua","family":"Mack","sequence":"first","affiliation":[{"name":"University of Arizona Department of Electrical &amp; Computer Engineering, Tucson, Arizona, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4574-9555","authenticated-orcid":false,"given":"Sahil","family":"Hassan","sequence":"additional","affiliation":[{"name":"University of Arizona Department of Electrical &amp; Computer Engineering, Tucson, Arizona, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1578-5504","authenticated-orcid":false,"given":"Nirmal","family":"Kumbhare","sequence":"additional","affiliation":[{"name":"University of Arizona Department of Electrical &amp; Computer Engineering, Tucson, Arizona, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3575-2320","authenticated-orcid":false,"given":"Miguel","family":"Castro Gonzalez","sequence":"additional","affiliation":[{"name":"University of Arizona Department of Electrical &amp; Computer Engineering, Tucson, Arizona, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7982-8991","authenticated-orcid":false,"given":"Ali","family":"Akoglu","sequence":"additional","affiliation":[{"name":"University of Arizona Department of Electrical &amp; Computer Engineering, Tucson, Arizona, USA"}]}],"member":"320","published-online":{"date-parts":[[2023,1,24]]},"reference":[{"key":"e_1_3_2_2_2","unstructured":"ARM AMBA. 2010. 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