{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,16]],"date-time":"2026-05-16T16:53:40Z","timestamp":1778950420912,"version":"3.51.4"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2022,7,31]],"date-time":"2022-07-31T00:00:00Z","timestamp":1659225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001869","name":"Academia Sinica","doi-asserted-by":"crossref","award":["AS-IA-111-M01, AS-GCS-110-08, and AS-CDA-107-M05"],"award-info":[{"award-number":["AS-IA-111-M01, AS-GCS-110-08, and AS-CDA-107-M05"]}],"id":[{"id":"10.13039\/501100001869","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Ministry of Science and Technology","award":["110-2223-E-001-001 and 110-2917-I-564-025"],"award-info":[{"award-number":["110-2223-E-001-001 and 110-2917-I-564-025"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2022,7,31]]},"abstract":"<jats:p>\n            In the big data era, a huge number of services has placed a fast-growing demand on the capacity of DRAM-based main memory. However, due to the high hardware cost and serious leakage power\/energy consumption, the growth rate of DRAM capacity cannot meet the increased rate of the required main memory space when the energy or hardware cost is a critical concern. To tackle this issue, hybrid main-memory devices\/modules have been proposed to replace the pure DRAM main memory with a hybrid main memory module that provides a large main memory space by integrating a small-sized DRAM and a large-sized\n            <jats:bold>non-volatile memory (NVM)<\/jats:bold>\n            into the same memory module. Although NVMs have high-density and low-cost features, they suffer from the low read\/write performance and low endurance issue, compared to DRAM. Thus, inside the hybrid main-memory module, it also includes a memory management design to use DRAM as the cache of NVMs to enhance its performance and lifetime. However, it also introduces new design challenges in both the OS and the memory module. In this work, we rethink the interactivity of OS and hybrid main-memory module, and propose a cross-layer cache design that (1) utilizes the information from the operating system to optimize the hit ratio of the DRAM cache inside the memory module, and (2) takes advantage of the bulk-size (or block-based) read\/write feature of NVM to minimize the time overhead on the data movement between DRAM and NVM. At the same time, this cross-layer cache design is very lightweight and only introduces limited runtime management overheads. A series of experiments was conducted to evaluate the effectiveness of the proposed cross-layer cache design. The results show that the proposed design could improve access performance for up to 88%, compared to the investigated well-known page replacement algorithms.\n          <\/jats:p>","DOI":"10.1145\/3530876","type":"journal-article","created":{"date-parts":[[2022,8,23]],"date-time":"2022-08-23T13:37:23Z","timestamp":1661261843000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Rethinking the Interactivity of OS and Device Layers in Memory Management"],"prefix":"10.1145","volume":"21","author":[{"given":"Tse-Yuan","family":"Wang","sequence":"first","affiliation":[{"name":"Academia Sinica, Nankang, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6367-0517","authenticated-orcid":false,"given":"Chun-Feng","family":"Wu","sequence":"additional","affiliation":[{"name":"Harvard University, Allston, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Che-Wei","family":"Tsao","sequence":"additional","affiliation":[{"name":"Academia Sinica, Nankang, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan-Hao","family":"Chang","sequence":"additional","affiliation":[{"name":"Academia Sinica, Nankang, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tei-Wei","family":"Kuo","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xue","family":"Liu","sequence":"additional","affiliation":[{"name":"McGill University, Montr\u00e9al Qu\u00e9bec, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,8,23]]},"reference":[{"key":"e_1_3_2_2_2","first-page":"187","volume-title":"Proceedings of the 3rd USENIX Conference on File and Storage Technologies (FAST\u201904)","author":"Bansal Sorav","year":"2004","unstructured":"Sorav Bansal and Dharmendra S. Modha. 2004. CAR: Clock with adaptive replacement. In Proceedings of the 3rd USENIX Conference on File and Storage Technologies (FAST\u201904). USENIX Association, Berkeley, CA, USA, 187\u2013200. http:\/\/dl.acm.org\/citation.cfm?id=1096673.1096699."},{"key":"e_1_3_2_3_2","article-title":"Leveraging write heterogeneity of phase change memory on supporting self-balancing binary tree","author":"Chang Che-Wei","year":"2021","unstructured":"Che-Wei Chang, Chun-Feng Wu, Yuan-Hao Chang, Ming-Chang Yang, and Chieh-Fu Chang. 2021. Leveraging write heterogeneity of phase change memory on supporting self-balancing binary tree. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2021).","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_4_2","first-page":"1","volume-title":"2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Chen R.","year":"2016","unstructured":"R. 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