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Most thermal management research is performed using simulations, given the challenges in measuring temperatures in real processors. Fast yet accurate interval thermal simulation toolchains remain the research tool of choice to study thermal management in processors at the system level. However, the existing toolchains focus on the thermal management of cores in the processors, since they exhibit much higher power densities than memory.<\/jats:p><jats:p>The memory bandwidth limitations associated with 2D processors lead to high-density 2.5D and 3D packaging technology: 2.5D packaging technology places cores and memory on the same package; 3D packaging technology takes it further by stacking layers of memory on the top of cores themselves. These new packagings significantly increase the power density of the processors, making them prone to overheating. Therefore, mitigating thermal issues in high-density processors (packaged with stacked memory) becomes even more pressing. However, given the lack of thermal modeling for memories in existing interval thermal simulation toolchains, they are unsuitable for studying thermal management for high-density processors.<\/jats:p><jats:p>To address this issue, we present the first integrated Core and Memory interval Thermal (<jats:italic>CoMeT<\/jats:italic>) simulation toolchain.<jats:italic>CoMeT<\/jats:italic>comprehensively supports thermal simulation of high- and low-density processors corresponding to four different core-memory (integration) configurations\u2014off-chip DDR memory, off-chip 3D memory, 2.5D, and 3D.<jats:italic>CoMeT<\/jats:italic>supports several novel features that facilitate overlying system research.<jats:italic>CoMeT<\/jats:italic>adds only an additional ~5% simulation-time overhead compared to an equivalent state-of-the-art core-only toolchain. The source code of<jats:italic>CoMeT<\/jats:italic>has been made open for public use under the<jats:italic>MIT<\/jats:italic>license.<\/jats:p>","DOI":"10.1145\/3532185","type":"journal-article","created":{"date-parts":[[2022,6,14]],"date-time":"2022-06-14T09:56:55Z","timestamp":1655200615000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":26,"title":["CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5312-8679","authenticated-orcid":false,"given":"Lokesh","family":"Siddhu","sequence":"first","affiliation":[{"name":"Department of CSE, Indian Institute of Technology Delhi, New Delhi, Delhi, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3711-0396","authenticated-orcid":false,"given":"Rajesh","family":"Kedia","sequence":"additional","affiliation":[{"name":"Department of CSE, Indian Institute of Technology Hyderabad, Kandi, Telangana, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3013-5128","authenticated-orcid":false,"given":"Shailja","family":"Pandey","sequence":"additional","affiliation":[{"name":"Department of CSE, Indian Institute of Technology Delhi, New Delhi, Delhi, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5989-2950","authenticated-orcid":false,"given":"Martin","family":"Rapp","sequence":"additional","affiliation":[{"name":"Chair for Embedded System (CES), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5813-7021","authenticated-orcid":false,"given":"Anuj","family":"Pathania","sequence":"additional","affiliation":[{"name":"Informatics Departments, University of Amsterdam, Amsterdam, Netherlands"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9602-2922","authenticated-orcid":false,"given":"J\u00f6rg","family":"Henkel","sequence":"additional","affiliation":[{"name":"Chair for Embedded System (CES), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2508-7531","authenticated-orcid":false,"given":"Preeti Ranjan","family":"Panda","sequence":"additional","affiliation":[{"name":"Department of CSE, Indian Institute of Technology Delhi, New Delhi, Delhi, India"}]}],"member":"320","published-online":{"date-parts":[[2022,8,22]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"crossref","unstructured":"Raid Ayoub Rajib Nath and Tajana Simunic Rosing. 2013. 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