{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T08:01:07Z","timestamp":1761897667965,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":31,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T00:00:00Z","timestamp":1654473600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,6]]},"DOI":"10.1145\/3534056.3534939","type":"proceedings-article","created":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T14:56:12Z","timestamp":1654527372000},"page":"1-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Eliminate the overhead of interrupt checking in full-system dynamic binary translator"],"prefix":"10.1145","author":[{"given":"Gen","family":"Niu","sequence":"first","affiliation":[{"name":"China University of Chinese Academy of Sciences, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fuxin","family":"Zhang","sequence":"additional","affiliation":[{"name":"China University of Chinese Academy of Sciences, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xinyu","family":"Li","sequence":"additional","affiliation":[{"name":"China University of Chinese Academy of Sciences, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,6,6]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"ARM Holdings 2013. ARM Generic Interrupt Controller Architecture version 2.0 - Architecture Specification. ARM Holdings. https:\/\/developer.arm.com\/documentation\/ihi0048\/latest.  ARM Holdings 2013. ARM Generic Interrupt Controller Architecture version 2.0 - Architecture Specification. ARM Holdings. https:\/\/developer.arm.com\/documentation\/ihi0048\/latest."},{"key":"e_1_3_2_1_2_1","volume-title":"Proceedings of the FREENIX Track: 2005 USENIX Annual Technical Conference, April 10--15","author":"Bellard Fabrice","year":"2005","unstructured":"Fabrice Bellard . 2005 . QEMU, a Fast and Portable Dynamic Translator . In Proceedings of the FREENIX Track: 2005 USENIX Annual Technical Conference, April 10--15 , 2005. USENIX, Anaheim, CA, USA, 41--46. http:\/\/www.usenix.org\/events\/usenix05\/tech\/freenix\/bellard.html Fabrice Bellard. 2005. QEMU, a Fast and Portable Dynamic Translator. In Proceedings of the FREENIX Track: 2005 USENIX Annual Technical Conference, April 10--15, 2005. USENIX, Anaheim, CA, USA, 41--46. http:\/\/www.usenix.org\/events\/usenix05\/tech\/freenix\/bellard.html"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.5555\/776261.776290"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.5555\/3092778"},{"key":"e_1_3_2_1_5_1","unstructured":"Jonathan Corbet. 2021. User-space interrupts. https:\/\/lwn.net\/Articles\/871113\/ [Online] Accessed on 2022-02-23.  Jonathan Corbet. 2021. User-space interrupts. https:\/\/lwn.net\/Articles\/871113\/ [Online] Accessed on 2022-02-23."},{"volume-title":"Proceedings of the 2017 International Symposium on Code Generation and Optimization","author":"Cota Emilio G.","key":"e_1_3_2_1_6_1","unstructured":"Emilio G. Cota , Paolo Bonzini , Alex Benn\u00e9e , and Luca P. Carloni . 2017. Cross-ISA Machine Emulation for Multicores . In Proceedings of the 2017 International Symposium on Code Generation and Optimization ( Austin, USA) (CGO '17). IEEE Press, 210\u00e2\u0102\u015e220. Emilio G. Cota, Paolo Bonzini, Alex Benn\u00e9e, and Luca P. Carloni. 2017. Cross-ISA Machine Emulation for Multicores. In Proceedings of the 2017 International Symposium on Code Generation and Optimization (Austin, USA) (CGO '17). IEEE Press, 210\u00e2\u0102\u015e220."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3313808.3313811"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2693433.2693437"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2003.1191529"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264126"},{"key":"e_1_3_2_1_11_1","unstructured":"EEMBC. 2009. CoreMark - An EEMBC Benchmark. https:\/\/www.eembc.org\/coremark\/index.php  EEMBC. 2009. CoreMark - An EEMBC Benchmark. https:\/\/www.eembc.org\/coremark\/index.php"},{"volume-title":"Detecting Unread Memory Using Dynamic Binary Translation","author":"Eyolfson Jon","key":"e_1_3_2_1_12_1","unstructured":"Jon Eyolfson and Patrick Lam . 2013. Detecting Unread Memory Using Dynamic Binary Translation . In Runtime Verification, Shaz Qadeer and Serdar Tasiran (Eds.). Springer Berlin Heidelberg , Berlin, Heidelberg , 49--63. Jon Eyolfson and Patrick Lam. 2013. Detecting Unread Memory Using Dynamic Binary Translation. In Runtime Verification, Shaz Qadeer and Serdar Tasiran (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 49--63."},{"volume-title":"Intel 64 and IA-32 Architectures Software Developer's Manual","author":"Intel Corporation 2021.","key":"e_1_3_2_1_13_1","unstructured":"Intel Corporation 2021. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3 Chapter 29.6 Posted-Interrupt Processing. Intel Corporation . https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/671447. Intel Corporation 2021. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3 Chapter 29.6 Posted-Interrupt Processing. Intel Corporation. https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/671447."},{"volume-title":"Intel 64 and IA-32 Architectures Software Developer's Manual","author":"Intel Corporation 2021.","key":"e_1_3_2_1_14_1","unstructured":"Intel Corporation 2021. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3 Chapter 8.1.3 Handling Self- and Cross-Modifying Code. Intel Corporation . https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/671447. Intel Corporation 2021. Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3 Chapter 8.1.3 Handling Self- and Cross-Modifying Code. Intel Corporation. https:\/\/cdrdv2.intel.com\/v1\/dl\/getContent\/671447."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETCS.2009.288"},{"key":"e_1_3_2_1_16_1","unstructured":"Loongson Technology 2021. LoongArch Documentation. Loongson Technology. https:\/\/loongson.github.io\/LoongArch-Documentation\/.  Loongson Technology 2021. LoongArch Documentation. Loongson Technology. https:\/\/loongson.github.io\/LoongArch-Documentation\/."},{"key":"e_1_3_2_1_17_1","unstructured":"Loongson Technology 2021. Loongson 3A5000\/3B5000 Product Manual. Loongson Technology. https:\/\/www.loongson.cn\/productShow\/32.  Loongson Technology 2021. Loongson 3A5000\/3B5000 Product Manual. Loongson Technology. https:\/\/www.loongson.cn\/productShow\/32."},{"key":"e_1_3_2_1_18_1","unstructured":"Mark Lord. 2012. hdparm - get\/set SATA\/IDE device parameters. https:\/\/linux.die.net\/man\/8\/hdparm  Mark Lord. 2012. hdparm - get\/set SATA\/IDE device parameters. https:\/\/linux.die.net\/man\/8\/hdparm"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_20_1","volume-title":"User Interrupts \u00e2\u0102\u015e A faster way to signal. https:\/\/lpc.events\/event\/11\/contributions\/985\/ LPC","author":"Mehta Sohil","year":"2021","unstructured":"Sohil Mehta . 2021. User Interrupts \u00e2\u0102\u015e A faster way to signal. https:\/\/lpc.events\/event\/11\/contributions\/985\/ LPC 2021 . Sohil Mehta. 2021. User Interrupts \u00e2\u0102\u015e A faster way to signal. https:\/\/lpc.events\/event\/11\/contributions\/985\/ LPC 2021."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2678022"},{"key":"e_1_3_2_1_22_1","unstructured":"Ingo Molnar. 2009. Performance Counters for Linux. https:\/\/lwn.net\/Articles\/337493\/ [Online] Accessed on 2022-02-23.  Ingo Molnar. 2009. Performance Counters for Linux. https:\/\/lwn.net\/Articles\/337493\/ [Online] Accessed on 2022-02-23."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1273442.1250746"},{"key":"e_1_3_2_1_24_1","volume-title":"SPEC CPU2000 benchmark suite. http:\/\/www.spec.org\/cpu2000\/","author":"SPEC.","year":"2000","unstructured":"SPEC. 2000 . SPEC CPU2000 benchmark suite. http:\/\/www.spec.org\/cpu2000\/ SPEC. 2000. SPEC CPU2000 benchmark suite. http:\/\/www.spec.org\/cpu2000\/"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/2907950.2907953"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/2996798"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3386161"},{"key":"e_1_3_2_1_28_1","unstructured":"GTK Development Team. 2021. Struct Tree. https:\/\/docs.gtk.org\/glib\/struct.Tree.html [Online] Accessed on 2022-02-23.  GTK Development Team. 2021. Struct Tree. https:\/\/docs.gtk.org\/glib\/struct.Tree.html [Online] Accessed on 2022-02-23."},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1145\/1941553.1941583"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316415"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/233013.233025"}],"event":{"name":"SYSTOR '22: The 15th ACM International Systems and Storage Conference","sponsor":["SIGOPS ACM Special Interest Group on Operating Systems","Technion Israel Institute of Technology","USENIX Assoc USENIX Assoc"],"location":"Haifa Israel","acronym":"SYSTOR '22"},"container-title":["Proceedings of the 15th ACM International Conference on Systems and Storage"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3534056.3534939","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3534056.3534939","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:00:09Z","timestamp":1750186809000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3534056.3534939"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,6]]},"references-count":31,"alternative-id":["10.1145\/3534056.3534939","10.1145\/3534056"],"URL":"https:\/\/doi.org\/10.1145\/3534056.3534939","relation":{},"subject":[],"published":{"date-parts":[[2022,6,6]]},"assertion":[{"value":"2022-06-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}