{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,22]],"date-time":"2026-07-22T16:16:44Z","timestamp":1784737004924,"version":"3.55.0"},"publisher-location":"New York, NY, USA","reference-count":67,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,7]],"date-time":"2022-06-07T00:00:00Z","timestamp":1654560000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-2008799"],"award-info":[{"award-number":["CCF-2008799"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,7]]},"DOI":"10.1145\/3534879.3534882","type":"proceedings-article","created":{"date-parts":[[2022,6,6]],"date-time":"2022-06-06T16:12:47Z","timestamp":1654531967000},"page":"127-139","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":38,"title":["A Closer Look at Intel Resource Director Technology (RDT)"],"prefix":"10.1145","author":[{"given":"Parul","family":"Sohal","sequence":"first","affiliation":[{"name":"Boston University, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael","family":"Bechtel","sequence":"additional","affiliation":[{"name":"University of Kansas, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Renato","family":"Mancuso","sequence":"additional","affiliation":[{"name":"Boston University, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Heechul","family":"Yun","sequence":"additional","affiliation":[{"name":"University of Kansas, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Orran","family":"Krieger","sequence":"additional","affiliation":[{"name":"Boston University, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,6,7]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/REAL.2002.1181563"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3012210"},{"key":"e_1_3_2_1_3_1","volume-title":"Outstanding Paper: Evaluation of Cache Partitioning for Hard Real-Time Systems. In 2014 26th Euromicro Conference on Real-Time Systems. IEEE, 15\u201326","author":"Altmeyer Sebastian","year":"2014","unstructured":"Sebastian Altmeyer , Roeland Douma , Will Lunniss , and Robert\u00a0 I Davis . 2014 . Outstanding Paper: Evaluation of Cache Partitioning for Hard Real-Time Systems. In 2014 26th Euromicro Conference on Real-Time Systems. IEEE, 15\u201326 . Sebastian Altmeyer, Roeland Douma, Will Lunniss, and Robert\u00a0I Davis. 2014. Outstanding Paper: Evaluation of Cache Partitioning for Hard Real-Time Systems. In 2014 26th Euromicro Conference on Real-Time Systems. IEEE, 15\u201326."},{"key":"e_1_3_2_1_4_1","unstructured":"The Linux\u00a0Kernel Archives. 2001. NO_HZ: Reducing Scheduling-Clock Ticks. https:\/\/www.kernel.org\/doc\/Documentation\/timers\/NO_HZ.txt. Accessed on 04.12.2022.  The Linux\u00a0Kernel Archives. 2001. NO_HZ: Reducing Scheduling-Clock Ticks. https:\/\/www.kernel.org\/doc\/Documentation\/timers\/NO_HZ.txt. Accessed on 04.12.2022."},{"key":"e_1_3_2_1_5_1","unstructured":"Arm. 2018-2020. Arm Architecture Reference Manual Supplement Memory System Resource Partitioning and Monitoring(MPAM) for Armv8-A. Accessed on 10.16.2020.  Arm. 2018-2020. Arm Architecture Reference Manual Supplement Memory System Resource Partitioning and Monitoring(MPAM) for Armv8-A. Accessed on 10.16.2020."},{"key":"e_1_3_2_1_6_1","unstructured":"Arm. 2020. ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition. Accessed on 10.16.2021.  Arm. 2020. ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition. Accessed on 10.16.2021."},{"key":"e_1_3_2_1_7_1","volume-title":"Denial-of-service Attacks on Shared Cache in Multicore: Analysis and Prevention. In 2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 357\u2013367","author":"Bechtel Michael","year":"2019","unstructured":"Michael Bechtel and Heechul Yun . 2019 . Denial-of-service Attacks on Shared Cache in Multicore: Analysis and Prevention. In 2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 357\u2013367 . Michael Bechtel and Heechul Yun. 2019. Denial-of-service Attacks on Shared Cache in Multicore: Analysis and Prevention. In 2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 357\u2013367."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3108044"},{"key":"e_1_3_2_1_9_1","volume-title":"Temporal Isolation on Multiprocessing Architectures. In Design Automation Conference (DAC). 274 \u2013 279","author":"Bui Dai","year":"2011","unstructured":"Dai Bui , Edward\u00a0 A. Lee , Isaac Liu , Hiren Patel , and Jan Reineke . 2011 . Temporal Isolation on Multiprocessing Architectures. In Design Automation Conference (DAC). 274 \u2013 279 . http:\/\/chess.eecs.berkeley.edu\/pubs\/839.html Dai Bui, Edward\u00a0A. Lee, Isaac Liu, Hiren Patel, and Jan Reineke. 2011. Temporal Isolation on Multiprocessing Architectures. In Design Automation Conference (DAC). 274 \u2013 279. http:\/\/chess.eecs.berkeley.edu\/pubs\/839.html"},{"key":"e_1_3_2_1_10_1","unstructured":"Intel Corporation. 2015. Intel\u00ae Resource Director Technology (Intel\u00ae RDT) Framework. https:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/resource-director-technology.html. Accessed on 03.09.2019.  Intel Corporation. 2015. Intel\u00ae Resource Director Technology (Intel\u00ae RDT) Framework. https:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/resource-director-technology.html. Accessed on 03.09.2019."},{"key":"e_1_3_2_1_11_1","unstructured":"Intel Corporation. 2019. Welcome to the intel-cmt-cat Wiki https:\/\/github.com\/intel\/intel-cmt-cat\/wiki. Accessed on 01.23.2022.  Intel Corporation. 2019. Welcome to the intel-cmt-cat Wiki https:\/\/github.com\/intel\/intel-cmt-cat\/wiki. Accessed on 01.23.2022."},{"key":"e_1_3_2_1_12_1","volume-title":"Improving Prediction Accuracy of Memory Interferences for Multicore Platforms. In 2019 IEEE Real-Time Systems Symposium (RTSS). IEEE, 246\u2013259","author":"Courtaud C\u00e9dric","year":"2019","unstructured":"C\u00e9dric Courtaud , Julien Sopena , Gilles Muller , and Daniel\u00a0Gracia P\u00e9rez . 2019 . Improving Prediction Accuracy of Memory Interferences for Multicore Platforms. In 2019 IEEE Real-Time Systems Symposium (RTSS). IEEE, 246\u2013259 . C\u00e9dric Courtaud, Julien Sopena, Gilles Muller, and Daniel\u00a0Gracia P\u00e9rez. 2019. Improving Prediction Accuracy of Memory Interferences for Multicore Platforms. In 2019 IEEE Real-Time Systems Symposium (RTSS). IEEE, 246\u2013259."},{"key":"e_1_3_2_1_13_1","volume-title":"BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. In 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 364\u2013375","author":"Farshchi Farzad","year":"2020","unstructured":"Farzad Farshchi , Qijing Huang , and Heechul Yun . 2020 . BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. In 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 364\u2013375 . https:\/\/doi.org\/10.1109\/RTAS48715.2020.00011 10.1109\/RTAS48715.2020.00011 Farzad Farshchi, Qijing Huang, and Heechul Yun. 2020. BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. In 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). 364\u2013375. https:\/\/doi.org\/10.1109\/RTAS48715.2020.00011"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS48715.2020.00011"},{"key":"#cr-split#-e_1_3_2_1_15_1.1","unstructured":"Farzad Farshchi Prathap\u00a0Kumar Valsan Renato Mancuso and Heechul Yun. 2018. Deterministic Memory Abstraction and Supporting Multicore System Architecture. In 30th Euromicro Conference on Real-Time Systems (ECRTS 2018) (Dagstuhl Germany) (Leibniz International Proceedings in Informatics (LIPIcs) Vol.\u00a0106) Sebastian Altmeyer (Ed.). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik Barcelona Spain 1:1-1:25. https:\/\/doi.org\/10.4230\/LIPIcs.ECRTS.2018.1 10.4230\/LIPIcs.ECRTS.2018.1"},{"key":"#cr-split#-e_1_3_2_1_15_1.2","unstructured":"Farzad Farshchi Prathap\u00a0Kumar Valsan Renato Mancuso and Heechul Yun. 2018. Deterministic Memory Abstraction and Supporting Multicore System Architecture. In 30th Euromicro Conference on Real-Time Systems (ECRTS 2018) (Dagstuhl Germany) (Leibniz International Proceedings in Informatics (LIPIcs) Vol.\u00a0106) Sebastian Altmeyer (Ed.). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik Barcelona Spain 1:1-1:25. https:\/\/doi.org\/10.4230\/LIPIcs.ECRTS.2018.1"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303977"},{"key":"e_1_3_2_1_17_1","volume-title":"Intel 3rd Gen Xeon Scalable (Ice Lake Sp) review: Generationally Big, competitively small. https:\/\/www.anandtech.com\/show\/16594\/intel-3rd-gen-xeon-scalable-review\/4","author":"Frumusanu Andrei","unstructured":"Andrei Frumusanu . 2021. Intel 3rd Gen Xeon Scalable (Ice Lake Sp) review: Generationally Big, competitively small. https:\/\/www.anandtech.com\/show\/16594\/intel-3rd-gen-xeon-scalable-review\/4 Andrei Frumusanu. 2021. Intel 3rd Gen Xeon Scalable (Ice Lake Sp) review: Generationally Big, competitively small. https:\/\/www.anandtech.com\/show\/16594\/intel-3rd-gen-xeon-scalable-review\/4"},{"key":"e_1_3_2_1_18_1","volume-title":"Governing with Insights: Towards Profile-Driven Cache Management of Black-Box Applications. In 33rd Euromicro Conference on Real-Time Systems (ECRTS","author":"Ghaemi Golsana","year":"2021","unstructured":"Golsana Ghaemi , Dharmesh Tarapore , and Renato Mancuso . 2021 . Governing with Insights: Towards Profile-Driven Cache Management of Black-Box Applications. In 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021). Schloss Dagstuhl-Leibniz-Zentrum f\u00fcr Informatik. Golsana Ghaemi, Dharmesh Tarapore, and Renato Mancuso. 2021. Governing with Insights: Towards Profile-Driven Cache Management of Black-Box Applications. In 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021). Schloss Dagstuhl-Leibniz-Zentrum f\u00fcr Informatik."},{"key":"e_1_3_2_1_19_1","volume-title":"DNA: Dynamic Resource Allocation for Soft Real-Time Multicore Systems. In 2021 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 196\u2013209","author":"Gifford Robert","year":"2021","unstructured":"Robert Gifford , Neeraj Gandhi , Linh Thi\u00a0Xuan Phan , and Andreas Haeberlen . 2021 . DNA: Dynamic Resource Allocation for Soft Real-Time Multicore Systems. In 2021 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 196\u2013209 . Robert Gifford, Neeraj Gandhi, Linh Thi\u00a0Xuan Phan, and Andreas Haeberlen. 2021. DNA: Dynamic Resource Allocation for Soft Real-Time Multicore Systems. In 2021 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 196\u2013209."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/2584655"},{"key":"e_1_3_2_1_21_1","unstructured":"Red Hat. 2011. Isolating CPUs Using Tuned-Profiles-Realtime. https:\/\/access.redhat.com\/documentation\/en-us\/red_hat_enterprise_linux_for_real_time\/7\/html\/tuning_guide\/isolating_cpus_using_tuned-profiles-realtime. Accessed on 01.23.2019.  Red Hat. 2011. Isolating CPUs Using Tuned-Profiles-Realtime. https:\/\/access.redhat.com\/documentation\/en-us\/red_hat_enterprise_linux_for_real_time\/7\/html\/tuning_guide\/isolating_cpus_using_tuned-profiles-realtime. Accessed on 01.23.2019."},{"key":"e_1_3_2_1_22_1","volume-title":"Introduction to Memory Bandwidth Allocation","author":"Cornu Andrew","year":"2019","unstructured":"Herdrich, Andrew J. and Cornu , Marcel and Abbasi , Khawar Munir . 2019. Introduction to Memory Bandwidth Allocation . Data Center Documentation (March 2019 ). https:\/\/software.intel.com\/en-us\/articles\/introduction-to-memory-bandwidth-allocation Accessed on 01.23.2021. Herdrich, Andrew J. and Cornu, Marcel and Abbasi, Khawar Munir. 2019. Introduction to Memory Bandwidth Allocation. Data Center Documentation (March 2019). https:\/\/software.intel.com\/en-us\/articles\/introduction-to-memory-bandwidth-allocation Accessed on 01.23.2021."},{"key":"e_1_3_2_1_23_1","unstructured":"Intel Cloud Technology. 2017. Are Noisy Neighbors in Your Data Center Keeping You Up at Night?Technical Report. Accessed on 08.11.2019.  Intel Cloud Technology. 2017. Are Noisy Neighbors in Your Data Center Keeping You Up at Night?Technical Report. Accessed on 08.11.2019."},{"key":"e_1_3_2_1_24_1","volume-title":"Intel 64 and IA-32 Architectures Software Developer\u2019s Manual","author":"Author Andi\u00a0Kleen Intel\u00a0Corporation","year":"2022","unstructured":"Author Andi\u00a0Kleen Intel\u00a0Corporation . 2009. Intel 64 and IA-32 Architectures Software Developer\u2019s Manual Volume 2A: Instruction Set Reference, A-M, 3- 180 CPUID reference. Accessed on 01.23. 2022 . Author Andi\u00a0Kleen Intel\u00a0Corporation. 2009. Intel 64 and IA-32 Architectures Software Developer\u2019s Manual Volume 2A: Instruction Set Reference, A-M, 3-180 CPUID reference. Accessed on 01.23.2022."},{"key":"e_1_3_2_1_25_1","unstructured":"IntelCorporation. 2016. Increasing Platform Determinism with Platform Quality of Service for the Data Plane Development Kit. 8\u20139 pages.  IntelCorporation. 2016. Increasing Platform Determinism with Platform Quality of Service for the Data Plane Development Kit. 8\u20139 pages."},{"key":"e_1_3_2_1_26_1","unstructured":"IntelCorporation. 2019. Intel 64 and IA-32 Architectures Software Developer\u2019s Manual (volume 3 ed.). 17\u201364\u201317\u201368 pages.  IntelCorporation. 2019. Intel 64 and IA-32 Architectures Software Developer\u2019s Manual (volume 3 ed.). 17\u201364\u201317\u201368 pages."},{"key":"e_1_3_2_1_27_1","volume-title":"Intel\u00ae Resource Director Technology (Intel\u00ae RDT) on 2nd Generation Intel\u00ae Xeon\u00ae Scalable Processors Reference Manual. 4\u201324 pages","author":"IntelCorporation","unstructured":"IntelCorporation . 2019. Intel\u00ae Resource Director Technology (Intel\u00ae RDT) on 2nd Generation Intel\u00ae Xeon\u00ae Scalable Processors Reference Manual. 4\u201324 pages . IntelCorporation. 2019. Intel\u00ae Resource Director Technology (Intel\u00ae RDT) on 2nd Generation Intel\u00ae Xeon\u00ae Scalable Processors Reference Manual. 4\u201324 pages."},{"key":"e_1_3_2_1_28_1","unstructured":"IntelCorporation. 2021. Intel\u00ae Architecture Instruction Set Extensions and Future Features. 10\u20132\u201310\u20134 pages.  IntelCorporation. 2021. Intel\u00ae Architecture Instruction Set Extensions and Future Features. 10\u20132\u201310\u20134 pages."},{"key":"e_1_3_2_1_29_1","volume-title":"Systematic Reverse Engineering of Cache Slice Selection in Intel Processors. In 2015 Euromicro Conference on Digital System Design. IEEE, 629\u2013636","author":"Irazoqui Gorka","year":"2015","unstructured":"Gorka Irazoqui , Thomas Eisenbarth , and Berk Sunar . 2015 . Systematic Reverse Engineering of Cache Slice Selection in Intel Processors. In 2015 Euromicro Conference on Digital System Design. IEEE, 629\u2013636 . Gorka Irazoqui, Thomas Eisenbarth, and Berk Sunar. 2015. Systematic Reverse Engineering of Cache Slice Selection in Intel Processors. In 2015 Euromicro Conference on Digital System Design. IEEE, 629\u2013636."},{"key":"e_1_3_2_1_30_1","volume-title":"Bounding Memory Interference Delay in COTS-based Multi-Core Systems. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 145\u2013154","author":"Kim Hyoseung","year":"2014","unstructured":"Hyoseung Kim , Dionisio De\u00a0Niz , Bj\u00f6rn Andersson , Mark Klein , Onur Mutlu , and Ragunathan Rajkumar . 2014 . Bounding Memory Interference Delay in COTS-based Multi-Core Systems. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 145\u2013154 . Hyoseung Kim, Dionisio De\u00a0Niz, Bj\u00f6rn Andersson, Mark Klein, Onur Mutlu, and Ragunathan Rajkumar. 2014. Bounding Memory Interference Delay in COTS-based Multi-Core Systems. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 145\u2013154."},{"key":"e_1_3_2_1_31_1","volume-title":"OSPERT 2014","author":"Kim Namhoon","year":"2014","unstructured":"Namhoon Kim , Jeremy\u00a0 P Erickson , and James\u00a0 H Anderson . 2014 . Mixed-criticality on Multicore (MC2): A Status Report . OSPERT 2014 (2014), 45. Namhoon Kim, Jeremy\u00a0P Erickson, and James\u00a0H Anderson. 2014. Mixed-criticality on Multicore (MC2): A Status Report. OSPERT 2014 (2014), 45."},{"key":"e_1_3_2_1_32_1","volume-title":"Cache Design for Mixed Criticality Real-Time Systems. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). IEEE, 513\u2013516","author":"Kumar G\u00a0Chetan","year":"2014","unstructured":"N G\u00a0Chetan Kumar , Sudhanshu Vyas , Ron\u00a0 K Cytron , Christopher\u00a0 D Gill , Joseph Zambreno , and Phillip\u00a0 H Jones . 2014 . Cache Design for Mixed Criticality Real-Time Systems. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). IEEE, 513\u2013516 . NG\u00a0Chetan Kumar, Sudhanshu Vyas, Ron\u00a0K Cytron, Christopher\u00a0D Gill, Joseph Zambreno, and Phillip\u00a0H Jones. 2014. Cache Design for Mixed Criticality Real-Time Systems. In 2014 IEEE 32nd International Conference on Computer Design (ICCD). IEEE, 513\u2013516."},{"key":"e_1_3_2_1_33_1","unstructured":"Linux. 2014. Performance Analysis Tools for Linux. Accessed on 01.23.2022.  Linux. 2014. Performance Analysis Tools for Linux. Accessed on 01.23.2022."},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446082"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3151891"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694382"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA.2016.7733567"},{"key":"e_1_3_2_1_39_1","volume-title":"Real-Time Cache Management Framework for Multi-Core Architectures. In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). 45\u201354","author":"Mancuso Renato","year":"2013","unstructured":"Renato Mancuso , Roman Dudko , Emiliano Betti , Marco Cesati , Marco Caccamo , and Rodolfo Pellizzoni . 2013 . Real-Time Cache Management Framework for Multi-Core Architectures. In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). 45\u201354 . https:\/\/doi.org\/10.1109\/RTAS.2013.6531078 10.1109\/RTAS.2013.6531078 Renato Mancuso, Roman Dudko, Emiliano Betti, Marco Cesati, Marco Caccamo, and Rodolfo Pellizzoni. 2013. Real-Time Cache Management Framework for Multi-Core Architectures. In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). 45\u201354. https:\/\/doi.org\/10.1109\/RTAS.2013.6531078"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2015.23"},{"key":"e_1_3_2_1_41_1","volume-title":"Impact of DM-LRU on WCET: A Static Analysis Approach. Leibniz international proceedings in informatics 133","author":"Mancuso Renato","year":"2019","unstructured":"Renato Mancuso , Heechul Yun , and Isabelle Puaut . 2019 . Impact of DM-LRU on WCET: A Static Analysis Approach. Leibniz international proceedings in informatics 133 (2019). Renato Mancuso, Heechul Yun, and Isabelle Puaut. 2019. Impact of DM-LRU on WCET: A Static Analysis Approach. Leibniz international proceedings in informatics 133 (2019)."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-26362-5_3"},{"key":"e_1_3_2_1_43_1","volume-title":"Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems. In USENIX Security Symposium. USENIX.","author":"Moscibroda Thomas","year":"2007","unstructured":"Thomas Moscibroda and Onur Mutlu . 2007 . Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems. In USENIX Security Symposium. USENIX. Thomas Moscibroda and Onur Mutlu. 2007. Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems. In USENIX Security Symposium. USENIX."},{"key":"e_1_3_2_1_44_1","volume-title":"31st Euromicro Conference on Real-Time Systems (ECRTS","author":"Pagani Marco","year":"2019","unstructured":"Marco Pagani , Enrico Rossi , Alessandro Biondi , Mauro Marinoni , Giuseppe Lipari , and Giorgio Buttazzo . 2019 . A Bandwidth Reservation Mechanism for AXI-based Hardware Accelerators on FPGAs . In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. Marco Pagani, Enrico Rossi, Alessandro Biondi, Mauro Marinoni, Giuseppe Lipari, and Giorgio Buttazzo. 2019. A Bandwidth Reservation Mechanism for AXI-based Hardware Accelerators on FPGAs. In 31st Euromicro Conference on Real-Time Systems (ECRTS 2019). Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik."},{"key":"e_1_3_2_1_45_1","unstructured":"Linux\u00a0Man Pages. 2004. numactl - Control NUMA policy for processes or shared memory. https:\/\/linux.die.net\/man\/8\/numactl. Accessed on 04.19.2019.  Linux\u00a0Man Pages. 2004. numactl - Control NUMA policy for processes or shared memory. https:\/\/linux.die.net\/man\/8\/numactl. Accessed on 04.19.2019."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303963"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2011.33"},{"key":"e_1_3_2_1_48_1","first-page":"69","volume":"49","author":"Sha Lui","year":"2016","unstructured":"Lui Sha , Marco Caccamo , Renato Mancuso , Jung-Eun Kim , Man-Ki Yoon , Rodolfo Pellizzoni , Heechul Yun , Russell\u00a0 B Kegley , Dennis\u00a0 R Perlman , Greg Arundale , 2016 . Real-time Computing on Multicore Processors. Computer 49 , 9 (2016), 69 \u2013 77 . Lui Sha, Marco Caccamo, Renato Mancuso, Jung-Eun Kim, Man-Ki Yoon, Rodolfo Pellizzoni, Heechul Yun, Russell\u00a0B Kegley, Dennis\u00a0R Perlman, Greg Arundale, 2016. Real-time Computing on Multicore Processors. Computer 49, 9 (2016), 69\u201377.","journal-title":"Real-time Computing on Multicore Processors. Computer"},{"key":"e_1_3_2_1_49_1","volume-title":"E-WarP: A System-Wide Framework for Memory Bandwidth Profiling and Management. In 2020 IEEE Real-Time Systems Symposium (RTSS). IEEE, 345\u2013357","author":"Sohal Parul","year":"2020","unstructured":"Parul Sohal , Rohan Tabish , Ulrich Drepper , and Renato Mancuso . 2020 . E-WarP: A System-Wide Framework for Memory Bandwidth Profiling and Management. In 2020 IEEE Real-Time Systems Symposium (RTSS). IEEE, 345\u2013357 . Parul Sohal, Rohan Tabish, Ulrich Drepper, and Renato Mancuso. 2020. E-WarP: A System-Wide Framework for Memory Bandwidth Profiling and Management. In 2020 IEEE Real-Time Systems Symposium (RTSS). IEEE, 345\u2013357."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830803"},{"key":"e_1_3_2_1_51_1","volume-title":"Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses. In 2013 IEEE 16th International Conference on Computational Science and Engineering. IEEE, 685\u2013692","author":"Suzuki Noriaki","year":"2013","unstructured":"Noriaki Suzuki , Hyoseung Kim , Dionisio De\u00a0Niz , Bjorn Andersson , Lutz Wrage , Mark Klein , and Ragunathan Rajkumar . 2013 . Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses. In 2013 IEEE 16th International Conference on Computational Science and Engineering. IEEE, 685\u2013692 . Noriaki Suzuki, Hyoseung Kim, Dionisio De\u00a0Niz, Bjorn Andersson, Lutz Wrage, Mark Klein, and Ragunathan Rajkumar. 2013. Coordinated Bank and Cache Coloring for Temporal Protection of Memory Accesses. In 2013 IEEE 16th International Conference on Computational Science and Engineering. IEEE, 685\u2013692."},{"key":"e_1_3_2_1_52_1","volume-title":"C-States, and Package C-States. Intel\u00ae Xeon Phi\u2122 Processor Documentation (April","author":"Kidd Taylor","year":"2014","unstructured":"Taylor IoT Kidd . 2014. Power Management States: P-States , C-States, and Package C-States. Intel\u00ae Xeon Phi\u2122 Processor Documentation (April 2014 ). https:\/\/software.intel.com\/en-us\/articles\/power-management-states-p-states-c-states-and-package-c-states Taylor IoT Kidd. 2014. Power Management States: P-States, C-States, and Package C-States. Intel\u00ae Xeon Phi\u2122 Processor Documentation (April 2014). https:\/\/software.intel.com\/en-us\/articles\/power-management-states-p-states-c-states-and-package-c-states"},{"key":"e_1_3_2_1_53_1","volume-title":"Tools for High Performance Computing","author":"Terpstra Dan","year":"2009","unstructured":"Dan Terpstra , Heike Jagode , Haihang You , and Jack Dongarra . 2010. Collecting performance data with PAPI-C . In Tools for High Performance Computing 2009 . Springer , 157\u2013173. Dan Terpstra, Heike Jagode, Haihang You, and Jack Dongarra. 2010. Collecting performance data with PAPI-C. In Tools for High Performance Computing 2009. Springer, 157\u2013173."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.78"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/2847255"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"publisher","DOI":"10.1109\/CPSNA.2015.24"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"e_1_3_2_1_58_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECRTS.2013.26"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.1145\/3337821.3337863"},{"key":"e_1_3_2_1_60_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317840"},{"key":"e_1_3_2_1_61_1","volume-title":"Analysis and Implementation of Global Preemptive Fixed-Priority Scheduling with Dynamic Cache Allocation. In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 1\u201312","author":"Xu Meng","year":"2016","unstructured":"Meng Xu , Linh Thi\u00a0Xuan Phan , Hyon-Young Choi , and Insup Lee . 2016 . Analysis and Implementation of Global Preemptive Fixed-Priority Scheduling with Dynamic Cache Allocation. In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 1\u201312 . Meng Xu, Linh Thi\u00a0Xuan Phan, Hyon-Young Choi, and Insup Lee. 2016. Analysis and Implementation of Global Preemptive Fixed-Priority Scheduling with Dynamic Cache Allocation. In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 1\u201312."},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2017.15"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2640961"},{"key":"e_1_3_2_1_64_1","volume-title":"PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 155\u2013166","author":"Yun Heechul","year":"2014","unstructured":"Heechul Yun , Renato Mancuso , Zheng-Pei Wu , and Rodolfo Pellizzoni . 2014 . PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 155\u2013166 . Heechul Yun, Renato Mancuso, Zheng-Pei Wu, and Rodolfo Pellizzoni. 2014. PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms. In 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 155\u2013166."},{"key":"e_1_3_2_1_65_1","volume-title":"Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems. In 2015 27th Euromicro Conference on Real-Time Systems. IEEE, 184\u2013195","author":"Yun Heechul","year":"2015","unstructured":"Heechul Yun , Rodolfo Pellizzon , and Prathap\u00a0Kumar Valsan . 2015 . Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems. In 2015 27th Euromicro Conference on Real-Time Systems. IEEE, 184\u2013195 . Heechul Yun, Rodolfo Pellizzon, and Prathap\u00a0Kumar Valsan. 2015. Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems. In 2015 27th Euromicro Conference on Real-Time Systems. IEEE, 184\u2013195."},{"key":"e_1_3_2_1_66_1","volume-title":"2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 55\u201364","author":"Yun Heechul","year":"2013","unstructured":"Heechul Yun , Gang Yao , Rodolfo Pellizzoni , Marco Caccamo , and Lui Sha . 2013 . Memguard: Memory bandwidth Reservation System for Efficient Performance Isolation in Multi-Core Platforms . In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 55\u201364 . Heechul Yun, Gang Yao, Rodolfo Pellizzoni, Marco Caccamo, and Lui Sha. 2013. Memguard: Memory bandwidth Reservation System for Efficient Performance Isolation in Multi-Core Platforms. In 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 55\u201364."},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001193"}],"event":{"name":"RTNS 2022: The 30th International Conference on Real-Time Networks and Systems","location":"Paris France","acronym":"RTNS 2022"},"container-title":["Proceedings of the 30th International Conference on Real-Time Networks and Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3534879.3534882","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3534879.3534882","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3534879.3534882","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:53Z","timestamp":1750186973000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3534879.3534882"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,7]]},"references-count":67,"alternative-id":["10.1145\/3534879.3534882","10.1145\/3534879"],"URL":"https:\/\/doi.org\/10.1145\/3534879.3534882","relation":{},"subject":[],"published":{"date-parts":[[2022,6,7]]},"assertion":[{"value":"2022-06-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}