{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T15:19:26Z","timestamp":1783610366681,"version":"3.55.0"},"reference-count":55,"publisher":"Association for Computing Machinery (ACM)","issue":"4","license":[{"start":{"date-parts":[[2022,7,31]],"date-time":"2022-07-31T00:00:00Z","timestamp":1659225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2022,7,31]]},"abstract":"<jats:p>Human Activity Recognition (HAR) based on inertial data is an increasingly diffused task on embedded devices, from smartphones to ultra low-power sensors. Due to the high computational complexity of deep learning models, most embedded HAR systems are based on simple and not-so-accurate classic machine learning algorithms. This work bridges the gap between on-device HAR and deep learning, proposing a set of efficient one-dimensional Convolutional Neural Networks (CNNs) that can be deployed on general purpose microcontrollers (MCUs). Our CNNs are obtained combining hyper-parameters optimization with sub-byte and mixed-precision quantization, to find good trade-offs between classification results and memory occupation. Moreover, we also leverage adaptive inference as an orthogonal optimization to tune the inference complexity at runtime based on the processed input, hence producing a more flexible HAR system.<\/jats:p>\n          <jats:p>With experiments on four datasets, and targeting an ultra-low-power RISC-V MCU, we show that (i) we are able to obtain a rich set of Pareto-optimal CNNs for HAR, spanning more than 1 order of magnitude in terms of memory, latency, and energy consumption; (ii) thanks to adaptive inference, we can derive &gt;20 runtime operating modes starting from a single CNN, differing by up to 10% in classification scores and by more than 3\u00d7 in inference complexity, with a limited memory overhead; (iii) on three of the four benchmarks, we outperform all previous deep learning methods, while reducing the memory occupation by more than 100\u00d7. The few methods that obtain better performance (both shallow and deep) are not compatible with MCU deployment; (iv) all our CNNs are compatible with real-time on-device HAR, achieving an inference latency that ranges between 9 \u03bcs and 16 ms. Their memory occupation varies in 0.05\u201323.17 kB, and their energy consumption in 0.05 and 61.59 \u03bcJ, allowing years of continuous operation on a small battery supply.<\/jats:p>","DOI":"10.1145\/3542819","type":"journal-article","created":{"date-parts":[[2022,8,23]],"date-time":"2022-08-23T13:37:23Z","timestamp":1661261843000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":49,"title":["Human Activity Recognition on Microcontrollers with Quantized and Adaptive Deep Neural Networks"],"prefix":"10.1145","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9595-7216","authenticated-orcid":false,"given":"Francesco","family":"Daghero","sequence":"first","affiliation":[{"name":"Politecnico di Torino, Turin, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6215-8220","authenticated-orcid":false,"given":"Alessio","family":"Burrello","sequence":"additional","affiliation":[{"name":"University of Bologna, Bologna, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9225-3106","authenticated-orcid":false,"given":"Chen","family":"Xie","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Turin, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7709-1356","authenticated-orcid":false,"given":"Marco","family":"Castellano","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Cornaredo, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7036-0560","authenticated-orcid":false,"given":"Luca","family":"Gandolfi","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Cornaredo, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5881-3811","authenticated-orcid":false,"given":"Andrea","family":"Calimera","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Turin, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9046-5618","authenticated-orcid":false,"given":"Enrico","family":"Macii","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Turin, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1369-9688","authenticated-orcid":false,"given":"Massimo","family":"Poncino","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Turin, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2872-7071","authenticated-orcid":false,"given":"Daniele Jahier","family":"Pagliari","sequence":"additional","affiliation":[{"name":"Politecnico di Torino, Turin, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2022,8,23]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2020.03.289"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-35395-6_30"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.3390\/s151229858"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1177\/0020294018813692"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2014.07.009"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2019.2920283"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/3387902.3394038"},{"key":"e_1_3_1_9_2","first-page":"1","volume-title":"Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED\u201921)","year":"2021","unstructured":"Alessio Burrello, Alberto Dequino, Daniele Jahier Pagliari, Francesco Conti, Marcello Zanghieri, Enrico Macii, Luca Benini, and Massimo Poncino. 2021. TCN mapping optimization for ultra-low power time-series edge inference. In Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED\u201921). 1\u20136."},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR42600.2020.00242"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2019.2921977"},{"key":"e_1_3_1_12_2","unstructured":"Retrieved from https:\/\/arXiv:1805.06085 2018 Pact: Parameterized clipping activation for quantized neural networks"},{"key":"e_1_3_1_13_2","doi-asserted-by":"crossref","unstructured":"Francesco Daghero Daniele Jahier Pagliari and Massimo Poncino. 2020. Energy-efficient deep learning inference on edge devices. In Advances in Computers . Vol. 122. Elsevier 247\u2013301.","DOI":"10.1016\/bs.adcom.2020.07.002"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/3457388.3458656"},{"key":"e_1_3_1_15_2","first-page":"3893","article-title":"A partially binarized hybrid neural network system for low-power and resource constrained human activity recognition","year":"2020","unstructured":"Antonio De Vita, Alessandro Russo, Danilo Pau, Luigi Di Benedetto, Alfredo Rubino, and Gian Domenico Licciardo 2020. A partially binarized hybrid neural network system for low-power and resource constrained human activity recognition. IEEE Trans. Circ. Syst. 67, 11 (2020), 3893\u20133904.","journal-title":"IEEE Trans. Circ. Syst."},{"issue":"11","key":"e_1_3_1_16_2","first-page":"3905","article-title":"Always-on 674 \\( \\mu \\)  W@ 4GOP\/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node","volume":"67","year":"2020","unstructured":"Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, and Luca Benini. 2020. Always-on 674 \\( \\mu \\) W@ 4GOP\/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node. IEEE Trans. Circ. Syst. 67, 11 (2020), 3905\u20133918.","journal-title":"IEEE Trans. Circ. Syst."},{"key":"e_1_3_1_17_2","first-page":"64","volume-title":"Proceedings of the International Conference on Advanced Cloud and Big Data","year":"2013","unstructured":"Lin Fan, Zhongmin Wang, and Hai Wang. 2013. Human activity recognition model based on decision tree. In Proceedings of the International Conference on Advanced Cloud and Big Data. IEEE, 64\u201368."},{"key":"e_1_3_1_18_2","unstructured":"Xitong Gao Yiren Zhao \u0141ukasz Dudziak Robert Mullins and Cheng-zhong Xu. 2018. Dynamic channel pruning: Feature boosting and suppression. Retrieved from http:\/\/arxiv.org\/abs\/1810.05331."},{"key":"e_1_3_1_19_2","first-page":"1586","volume-title":"Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition","year":"2018","unstructured":"Ariel Gordon, Elad Eban, Ofir Nachum, Bo Chen, Hao Wu, Tien-Ju Yang, and Edward Choi. 2018. MorphNet: Fast & simple resource-constrained structure learning of deep networks. In Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition. 1586\u20131595."},{"key":"e_1_3_1_20_2","unstructured":"Chuan Guo Geoff Pleiss Yu Sun and Kilian Q. Weinberger. 2017. On calibration of modern neural networks. Retrieved from https:\/\/arxiv.org\/abs\/1706.04599."},{"key":"e_1_3_1_21_2","first-page":"1533","volume-title":"Proceedings of the 25th International Joint Conference on Artificial Intelligence","year":"2016","unstructured":"Nils Y. Hammerla, Shane Halloran, and Thomas Pl\u00f6tz. 2016. Deep, convolutional, and recurrent models for human activity recognition using wearables. In Proceedings of the 25th International Joint Conference on Artificial Intelligence. 1533\u20131540."},{"key":"e_1_3_1_22_2","unstructured":"Yizeng Han Gao Huang Shiji Song Le Yang Honghui Wang and Yulin Wang. 2021. Dynamic neural networks: A survey. Retrieved from https:\/\/arxiv.org\/abs\/2102.04906."},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3122298"},{"key":"e_1_3_1_24_2","first-page":"1","volume-title":"Proceedings of the 8th Mediterranean Conference on Embedded Computing (MECO\u201919)","year":"2019","unstructured":"Roland H\u00f6ller, Dominic Haselberger, Dominik Ballek, Peter R\u00f6ssler, Markus Krapfenbauer, and Martin Linauer. 2019. Open-source risc-v processor ip cores for fpgas\u2013overview and evaluation. In Proceedings of the 8th Mediterranean Conference on Embedded Computing (MECO\u201919). IEEE, 1\u20136."},{"key":"e_1_3_1_25_2","first-page":"4114","volume-title":"Advances in Neural Information Processing Systems","author":"Hubara Itay","year":"2016","unstructured":"Itay Hubara, Matthieu Courbariaux, Daniel Soudry, Ran El-Yaniv, and Yoshua Bengio. 2016. Binarized neural networks. In Advances in Neural Information Processing Systems. 4114\u20134122. Retrieved from https:\/\/arxiv.org\/abs\/1602.02505."},{"key":"e_1_3_1_26_2","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR\u201918)","year":"2018","unstructured":"Benoit Jacob, Skirmantas Kligys, Bo Chen, Menglong Zhu, Matthew Tang, Andrew Howard, Hartwig Adam, and Dmitry Kalenichenko. 2018. Quantization and training of neural networks for efficient integer-arithmetic-only inference. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition (CVPR\u201918). IEEE."},{"key":"e_1_3_1_27_2","first-page":"47:1\u201347:6","volume-title":"Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED\u201918)","year":"2018","unstructured":"Daniele Jahier Pagliari, Enrico Macii, and Massimo Poncino. 2018. Dynamic bit-width reconfiguration for energy-efficient deep learning hardware. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED\u201918). ACM, 47:1\u201347:6."},{"key":"e_1_3_1_28_2","first-page":"337","article-title":"Sequence-to-sequence neural networks inference on embedded processors using dynamic beam search","year":"2020","unstructured":"Daniele Jahier Pagliari, Francesco Daghero, and Massimo Poncino. 2020. Sequence-to-sequence neural networks inference on embedded processors using dynamic beam search. Electronics (2020), 337.","journal-title":"Electronics"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIP.2020.3018269"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/1964897.1964918"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"e_1_3_1_32_2","unstructured":"Ltd LiPol Battery Co.2021. LP201020 Datasheet. Retrieved from https:\/\/www.lipobatteries.net\/wp-content\/uploads\/2021\/11\/LP201020.pdf."},{"key":"e_1_3_1_33_2","unstructured":"IEEE Embed. Syst. Lett. 2021 Efficient transform algorithms for parallel ultra-low-power IoT end nodes"},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.3390\/app7101101"},{"key":"e_1_3_1_35_2","first-page":"8080","volume-title":"Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition","year":"2018","unstructured":"Ravi Teja Mullapudi, William R. Mark, Noam Shazeer, and Kayvon Fatahalian. 2018. Hydranets: Specialized dynamic architectures for efficient inference. In Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition. 8080\u20138089."},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.5555\/2830840.2830854"},{"key":"e_1_3_1_37_2","volume-title":"Advances in Neural Information Processing Systems 32","year":"2019","unstructured":"Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, et\u00a0al. 2019. PyTorch: An imperative style, high-performance deep learning library. In Advances in Neural Information Processing Systems 32. Curran Associates."},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.5555\/1953048.2078195"},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2015.07.085"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586187"},{"key":"e_1_3_1_41_2","first-page":"1","volume-title":"Proceedings of the IEEE Hot Chips 27 Symposium (HCS\u201915)","year":"2015","unstructured":"Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. 2015. PULP: A parallel ultra low power platform for next generation IoT applications. In Proceedings of the IEEE Hot Chips 27 Symposium (HCS\u201915). IEEE, 1\u201339."},{"key":"e_1_3_1_42_2","unstructured":"SiFive. 2021. SiFive Core IP. Retrieved from https:\/\/www.sifive.com\/risc-v-core-ip."},{"key":"e_1_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1145\/3126858.3126859"},{"key":"e_1_3_1_44_2","unstructured":"STMicroelectronics. 2019. iNEMO Inertial Module: Always-on 3D Accelerometer and 3D Gyroscope. Retrieved from www.st.com\/resource\/en\/datasheet\/lsm6dsox.pdf."},{"key":"e_1_3_1_45_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2020.3015521"},{"key":"e_1_3_1_46_2","first-page":"1","volume-title":"Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ ISSS\u201916)","year":"2016","unstructured":"Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, and Sherief Reda. 2016. Runtime configurable deep neural networks for energy-accuracy trade-off. In Proceedings of the International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ ISSS\u201916). IEEE, 1\u201310."},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICPR.2016.7900006"},{"key":"e_1_3_1_48_2","unstructured":"The PULP Platform. 2020. GVSOC: PULP Virtual Platform. Retrieved from https:\/\/github.com\/pulp-platform\/gvsoc."},{"key":"e_1_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.5220\/0005792401430151"},{"key":"e_1_3_1_50_2","first-page":"1","volume-title":"Proceedings of the 2nd International Conference on Information and Communication Technology for Competitive Strategies","year":"2016","unstructured":"K. H. Walse, Rajiv V. Dharaskar, and Vilas M. Thakare. 2016. Performance evaluation of classifiers on WISDM dataset for human activity recognition. In Proceedings of the 2nd International Conference on Information and Communication Technology for Competitive Strategies. 1\u20137."},{"key":"e_1_3_1_51_2","doi-asserted-by":"crossref","unstructured":"Alvin Wan Xiaoliang Dai Peizhao Zhang Zijian He Yuandong Tian Saining Xie Bichen Wu Matthew Yu Tao Xu Kan Chen et\u00a0al. 2020. FBNetV2: Differentiable Neural Architecture Search for Spatial and Channel Dimensions. In Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition . 12965\u201312974.","DOI":"10.1109\/CVPR42600.2020.01298"},{"key":"e_1_3_1_52_2","volume-title":"Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR\u201919)","year":"2019","unstructured":"Kuan Wang, Zhijian Liu, Yujun Lin, Ji Lin, and Song Han. 2019. HAQ: Hardware-aware automated quantization with mixed precision. In Proceedings of the IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR\u201919)."},{"key":"e_1_3_1_53_2","unstructured":"Andrew Waterman Yunsup Lee David A. Patterson and Krste Asanovi. 2016. The RISC-V instruction set manual volume I: User-level ISA version 2.1. https:\/\/apps.dtic.mil\/sti\/pdfs\/ADA605735.pdf."},{"key":"e_1_3_1_54_2","unstructured":"Jiahui Yu Linjie Yang Ning Xu Jianchao Yang and Thomas Huang. 2018. Slimmable neural networks. Retrieved from https:\/\/arXiv:1812.08928."},{"issue":"5","key":"e_1_3_1_55_2","first-page":"1","article-title":"TF-net: Deploying sub-byte deep neural networks on microcontrollers","volume":"18","year":"2019","unstructured":"Jiecao Yu, Andrew Lukefahr, Reetuparna Das, and Scott Mahlke. 2019. TF-net: Deploying sub-byte deep neural networks on microcontrollers. ACM Trans. Embed. Comput. Syst. 18, 5s (2019), 1\u201321.","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"e_1_3_1_56_2","volume-title":"Proceedings of the International Joint Conference on Neural Networks (IJCNN\u201920)","year":"2020","unstructured":"Yong Yuan, Chen Chen, Xiyuan Hu, and Silong Peng. 2020. EvoQ: Mixed precision quantization of DNNs via sensitivity guided evolutionary search. In Proceedings of the International Joint Conference on Neural Networks (IJCNN\u201920)."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3542819","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3542819","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:22Z","timestamp":1750186942000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3542819"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7,31]]},"references-count":55,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2022,7,31]]}},"alternative-id":["10.1145\/3542819"],"URL":"https:\/\/doi.org\/10.1145\/3542819","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7,31]]},"assertion":[{"value":"2022-02-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-05-01","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-08-23","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}