{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:14:34Z","timestamp":1750220074334,"version":"3.41.0"},"reference-count":28,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2022,12,10]],"date-time":"2022-12-10T00:00:00Z","timestamp":1670630400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2023,1,31]]},"abstract":"<jats:p>\n            With increasing design complexity, the portability of tests across different designs and platforms becomes a key criterion for accelerating verification closure. The Portable Test and Stimulus Standard (PSS) is an emerging industry standard prepared by Accellera for system-on-chip verification and testing. It provides language constructs to create a target-agnostic representation of stimulus and test scenarios reused by various users across many levels of integration. In this article, we present\n            <jats:sans-serif>CoVerPlan<\/jats:sans-serif>\n            , a comprehensive verification framework built to explore the power of action inferencing on test models written in PSS. The proposed verification framework leverages a Boolean satisfiability problem planner to unwind the actual verification flow from the PSS specifications and automatically synthesizes target-specific constraint-random testbenches and formal assertions.\n            <jats:sans-serif>CoVerPlan<\/jats:sans-serif>\n            also carries out assertion-based verification of the synthesized properties. We demonstrate the efficacy of our proposed framework over several case studies, like the Advanced Microcontroller Bus Architecture advanced peripheral bus protocol, a simple Reduced Instruction Set Computer processor, and a cache coherence protocol.\n          <\/jats:p>","DOI":"10.1145\/3543175","type":"journal-article","created":{"date-parts":[[2022,6,11]],"date-time":"2022-06-11T22:42:07Z","timestamp":1654987327000},"page":"1-32","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["CoVerPlan: A\n            <u>Co<\/u>\n            mprehensive\n            <u>Ver<\/u>\n            ification\n            <u>Plan<\/u>\n            ning Framework Leveraging PSS Specifications"],"prefix":"10.1145","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9514-141X","authenticated-orcid":false,"given":"Sourav","family":"Das","sequence":"first","affiliation":[{"name":"Indian Institute of Technology Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6652-9113","authenticated-orcid":false,"given":"Sayandeep","family":"Sanyal","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2076-3577","authenticated-orcid":false,"given":"Aritra","family":"Hazra","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2178-8154","authenticated-orcid":false,"given":"Pallab","family":"Dasgupta","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Kharagpur, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,12,10]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/IEEESTD.2007.4408637"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/IEEESTD.2018.8299595"},{"key":"e_1_3_2_4_2","volume-title":"Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications","author":"Biere A.","year":"2009","unstructured":"A. Biere, M. Heule, H. van Maaren, and T. Walsh2009. Handbook of Satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications. IOS Press, NLD."},{"volume-title":"AMBA APB Protocol Specification v2.0(D). ARM Limited.","year":"2017","key":"e_1_3_2_5_2","unstructured":"ARM. 2017. AMBA APB Protocol Specification v2.0(D). ARM Limited. Retrieved from https:\/\/developer.arm.com\/documentation\/ihi0024\/latest\/."},{"key":"e_1_3_2_6_2","volume-title":"Focus Your Use of Portable Stimulus on Three Key Axes.","author":"Ballance Matthew","year":"2019","unstructured":"Matthew Ballance. 2019. Focus Your Use of Portable Stimulus on Three Key Axes. Retrieved from https:\/\/www.techdesignforums.com\/practice\/technique\/how-to-use-three-axes-of-reuse-to-focus-portable-stimulus\/."},{"key":"e_1_3_2_7_2","volume-title":"Design and Verification Conference","author":"Bartley Mike","year":"2019","unstructured":"Mike Bartley. 2019. PSS: The promises and pitfalls of early adoption. In Design and Verification Conference."},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011276507260"},{"key":"e_1_3_2_9_2","volume-title":"Portable Stimulus and UVM.","author":"Fitzpatrick Tom","year":"2019","unstructured":"Tom Fitzpatrick. 2019. Portable Stimulus and UVM. Retrieved from https:\/\/www.techdesignforums.com\/practice\/technique\/portable-stimulus-and-uvm\/."},{"key":"e_1_3_2_10_2","volume-title":"Design and Verification Conference","author":"Bhatnagar David Brownell Gaurav","year":"2018","unstructured":"David Brownell Gaurav Bhatnagar. 2018. Portable stimulus vs formal vs UVM. A comparative analysis of verification methodologies throughout the life of an IP block. In Design and Verification Conference."},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICMETE.2016.67"},{"key":"e_1_3_2_12_2","volume-title":"Design and Verification Conference","author":"Hamid Adnan","year":"2016","unstructured":"Adnan Hamid, David Koogler, and Thomas L. Anderson. 2016. Using portable stimulus to verify cache coherency in many-core soc. In Design and Verification Conference."},{"key":"e_1_3_2_13_2","volume-title":"Computer Architecture. A Quantitative Approach (5th edition ed.)","author":"Hennessy John L.","year":"2012","unstructured":"John L. Hennessy and David A. Patterson.2012. Computer Architecture. A Quantitative Approach (5th edition ed.)."},{"key":"e_1_3_2_14_2","volume-title":"Computer Organisation and Design, the Hardware Software Interface (5th ed.)","author":"Hennessy John L.","year":"2014","unstructured":"John L. Hennessy and David A. Patterson. 2014. Computer Organisation and Design, the Hardware Software Interface (5th ed.)."},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2018.00015"},{"key":"e_1_3_2_16_2","unstructured":"Accellera Systems Initiative. 2021. Portable Test and Stimulus 2.0a Language Reference Manual. Retrieved from https:\/\/www.accellera.org\/images\/downloads\/standards\/Portable_Test_Stimulus_Standard_v20.pdf."},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2019.0283"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVDAT.2016.8064887"},{"key":"e_1_3_2_19_2","volume-title":"Design and Verification Conference","author":"Kim Dayoung","year":"2020","unstructured":"Dayoung Kim, Jaehun Lee, and Daeseo Cha. 2020. Post silicon performance validation using PSS. In Design and Verification Conference."},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45069-6_1"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.7717\/peerj-cs.103"},{"key":"e_1_3_2_22_2","volume-title":"Design and Verification Conference","author":"Rosenberg Sharon","year":"2019","unstructured":"Sharon Rosenberg. 2019. The powerful synergy between UVM and PSS. In Design and Verification Conference."},{"key":"e_1_3_2_23_2","volume-title":"Artificial Intelligence: A Modern Approach.","author":"Russel Stuart J.","year":"1995","unstructured":"Stuart J. Russel and Peter Norvig.1995. Artificial Intelligence: A Modern Approach.Alan APt, 335\u2013412."},{"key":"e_1_3_2_24_2","volume-title":"Design and Verification Conference","author":"Singh Simranjit","year":"2021","unstructured":"Simranjit Singh, Ashwani Aggarwal, Harshita Prabha, Vishnu Ramadas, Seonil Brian Choi, and Woojoo Space Kim. 2021. Adopting accellera\u2019s portable stimulus standard: Early development and validation using virtual prototyping. In Design and Verification Conference."},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2009.5351246"},{"key":"e_1_3_2_26_2","volume-title":"Design and Verification Conference","author":"Vasu Suresh","year":"2021","unstructured":"Suresh Vasu, Nithin Venkatesh, and Joydeep Maitra. 2021. Media performance validation in emulation and post silicon using portable stimulus standard. In Design and Verification Conference."},{"key":"e_1_3_2_27_2","volume-title":"Design and Verification Conference","author":"Venkatesan Swami","year":"2021","unstructured":"Swami Venkatesan. 2021. Strategies and methods of using PSS2.0 high level modeling techniques to augment UVM verification. In Design and Verification Conference."},{"key":"e_1_3_2_28_2","unstructured":"Wikipedia. 2002. Harvard Architecture. Retrieved from https:\/\/en.wikipedia.org\/wiki\/Harvard_architecture."},{"key":"e_1_3_2_29_2","volume-title":"Design and Verification Conference","author":"Wu Xia","year":"2020","unstructured":"Xia Wu, Jacob Sander Andersen, and Ole Kristoffersen. 2020. Does it pay off to add portable stimulus layer on top of UVM IP block test bench? In Design and Verification Conference."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543175","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3543175","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T18:09:16Z","timestamp":1750183756000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543175"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12,10]]},"references-count":28,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2023,1,31]]}},"alternative-id":["10.1145\/3543175"],"URL":"https:\/\/doi.org\/10.1145\/3543175","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"type":"print","value":"1084-4309"},{"type":"electronic","value":"1557-7309"}],"subject":[],"published":{"date-parts":[[2022,12,10]]},"assertion":[{"value":"2022-01-22","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-05-23","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-12-10","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}