{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T01:42:56Z","timestamp":1773193376208,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,2,12]],"date-time":"2023-02-12T00:00:00Z","timestamp":1676160000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,2,12]]},"DOI":"10.1145\/3543622.3573185","type":"proceedings-article","created":{"date-parts":[[2023,2,10]],"date-time":"2023-02-10T23:15:13Z","timestamp":1676070913000},"page":"3-13","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9171-3054","authenticated-orcid":false,"given":"Linus Y.","family":"Wong","sequence":"first","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jialiang","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5139-938X","authenticated-orcid":false,"given":"Jing (Jane)","family":"Li","sequence":"additional","affiliation":[{"name":"University of Pennsylvania, Philadelphia, PA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,2,12]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"229","volume-title":"FPGA '18","author":"Zhang J.","unstructured":"J. Zhang and J. Li, \"Degree-aware hybrid graph traversal on FPGA-HMC platform,\" in Proceedings of the 2018 ACM\/SIGDA International Symposium on Field- Programmable Gate Arrays, FPGA '18, (New York, NY, USA), p. 229--238, Association for Computing Machinery, 2018."},{"key":"e_1_3_2_1_2_1","first-page":"69","volume-title":"FPGA '21","author":"Chen X.","unstructured":"X. Chen, H. Tan, Y. Chen, B. He, W.-F. Wong, and D. Chen, \"ThunderGP: HLSbased graph processing framework on FPGAs,\" in The 2021 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '21, (New York, NY, USA), p. 69--80, Association for Computing Machinery, 2021."},{"key":"e_1_3_2_1_3_1","first-page":"1","volume-title":"GraphLily: Accelerating graph linear algebra on HBM-equipped FPGAs,\" in 2021 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","author":"Hu Y.","year":"2021","unstructured":"Y. Hu, Y. Du, E. Ustun, and Z. Zhang, \"GraphLily: Accelerating graph linear algebra on HBM-equipped FPGAs,\" in 2021 IEEE\/ACM International Conference On Computer Aided Design (ICCAD), pp. 1--9, 2021."},{"key":"e_1_3_2_1_4_1","first-page":"51","volume-title":"FPGA '20","author":"Li J.","unstructured":"J. Li, Y. Chi, and J. Cong, \"HeteroHalide: From image processing DSL to efficient FPGA acceleration,\" in Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '20, (New York, NY, USA), p. 51--57, Association for Computing Machinery, 2020."},{"key":"e_1_3_2_1_5_1","first-page":"251","volume-title":"FPGA '21","author":"Conficconi D.","unstructured":"D. Conficconi, E. D'Arnese, E. Del Sozzo, D. Sciuto, and M. D. Santambrogio, \"A framework for customizable FPGA-based image registration accelerators,\" in The 2021 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '21, (New York, NY, USA), p. 251--261, Association for Computing Machinery, 2021."},{"key":"e_1_3_2_1_6_1","first-page":"25","volume-title":"FPGA '17","author":"Zhang J.","unstructured":"J. Zhang and J. Li, \"Improving the performance of OpenCL-based FPGA accelerator for convolutional neural network,\" in Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '17, (New York, NY, USA), p. 25--34, Association for Computing Machinery, 2017."},{"key":"e_1_3_2_1_7_1","first-page":"101","volume-title":"FPGA '22","author":"Wang E.","unstructured":"E. Wang, J. J. Davis, G.-I. Stavrou, P. Y. K. Cheung, G. A. Constantinides, and M. Abdelfattah, \"Logic shrinkage: Learned FPGA netlist sparsity for efficient neural network inference,\" in Proceedings of the 2022 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '22, (New York, NY, USA), p. 101--111, Association for Computing Machinery, 2022."},{"key":"e_1_3_2_1_8_1","first-page":"55","volume-title":"FPGA '14","author":"Jun S.-W.","unstructured":"S.-W. Jun, M. Liu, K. E. Fleming, and Arvind, \"Scalable multi-access flash store for big data analytics,\" in Proceedings of the 2014 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, (New York, NY, USA), p. 55--64, Association for Computing Machinery, 2014."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"crossref","unstructured":"S.-W. Jun S. Xu and Arvind \"Terabyte sort on FPGA-accelerated flash storage \" in 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) pp. 17--24 2017.","DOI":"10.1109\/FCCM.2017.53"},{"key":"e_1_3_2_1_10_1","first-page":"379","volume-title":"WA)","author":"Ruan Z.","year":"2019","unstructured":"Z. Ruan, T. He, and J. Cong, \"INSIDER: Designing in-storage computing system for emerging high-performance drive,\" in 2019 USENIX Annual Technical Conference (USENIX ATC 19), (Renton, WA), pp. 379--394, USENIX Association, July 2019."},{"key":"e_1_3_2_1_11_1","first-page":"282","volume-title":"Bonsai: High performance adaptive merge tree sorting,\" in 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)","author":"Samardzic N.","year":"2020","unstructured":"N. Samardzic, W. Qiao, V. Aggarwal, M.-C. F. Chang, and J. Cong, \"Bonsai: High performance adaptive merge tree sorting,\" in 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), pp. 282--294, 2020."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.3009347"},{"key":"e_1_3_2_1_13_1","first-page":"2022","article-title":"NASCENT2: Generic near-storage sort accelerator for data analytics on SmartSSD","volume":"15","author":"Salamat S.","unstructured":"S. Salamat, H. Zhang, Y. S. Ki, and T. Rosing, \"NASCENT2: Generic near-storage sort accelerator for data analytics on SmartSSD,\" ACM Trans. Reconfigurable Technol. Syst., vol. 15, jan 2022.","journal-title":"ACM Trans. Reconfigurable Technol. Syst."},{"key":"e_1_3_2_1_14_1","first-page":"106","volume-title":"FANS: FPGA-accelerated near-storage sorting,\" in 2021 IEEE 29th Annual International Symposium on Field- Programmable Custom Computing Machines (FCCM)","author":"Qiao W.","year":"2021","unstructured":"W. Qiao, J. Oh, L. Guo, M.-C. F. Chang, and J. Cong, \"FANS: FPGA-accelerated near-storage sorting,\" in 2021 IEEE 29th Annual International Symposium on Field- Programmable Custom Computing Machines (FCCM), pp. 106--114, 2021."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"crossref","unstructured":"M. Soltaniyeh V. L. Moutinho Dos Reis M. Bryson R. Martin and S. Nagarakatte \"Near-storage acceleration of database query processing with SmartSSDs \" in 2021 IEEE 29th Annual International Symposium on Field- Programmable Custom Computing Machines (FCCM) pp. 265--265 2021.","DOI":"10.1109\/FCCM51124.2021.00052"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2021.3081752"},{"key":"e_1_3_2_1_17_1","unstructured":"AMD\/Xilinx \"Vitis high-level synthesis user guide (ug1399) \" 2021."},{"key":"e_1_3_2_1_18_1","unstructured":"ARM \"AMBA AXI and ACE protocol specification \" 2021."},{"key":"e_1_3_2_1_19_1","first-page":"1","volume-title":"Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks,\" in 2016 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Zhang C.","year":"2016","unstructured":"C. Zhang, Z. Fang, P. Zhou, P. Pan, and J. Cong, \"Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks,\" in 2016 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1--8, 2016."},{"key":"e_1_3_2_1_20_1","unstructured":"NVM Express Workgroup \"NVM Express 1.0e \" 2013."},{"issue":"1","key":"e_1_3_2_1_21_1","first-page":"x4","article-title":"DC P4610 series 1.6TB, 2.5","volume":"3","year":"2018","unstructured":"Solidigm, \"DC P4610 series 1.6TB, 2.5in PCIe 3.1 x4, 3D2, TLC,\" 2018.","journal-title":"PCIe"},{"key":"e_1_3_2_1_22_1","unstructured":"AMD\/Xilinx \"Xilinx runtime (XRT) release notes (ug1451) \" 2021."},{"key":"e_1_3_2_1_23_1","volume-title":"Getting started (ug910)","year":"2020","unstructured":"AMD\/Xilinx, \"Vivado design suite user guide: Getting started (ug910),\" 2020."},{"key":"e_1_3_2_1_24_1","volume-title":"Application acceleration development (ug1393)","year":"2021","unstructured":"AMD\/Xilinx, \"Vitis unified software platform documentation: Application acceleration development (ug1393),\" 2021."},{"key":"e_1_3_2_1_25_1","unstructured":"AMD\/Xilinx \"Vitis accelerated libraries \" 2021."},{"key":"e_1_3_2_1_26_1","volume-title":"Feb","author":"Zhou Y.","year":"2018","unstructured":"Y. Zhou, U. Gupta, S. Dai, R. Zhao, N. Srivastava, H. Jin, J. Featherston, Y.-H. Lai, G. Liu, G. A. Velasquez, W. Wang, and Z. Zhang, \"Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software-Programmable FPGAs,\" Int'l Symp. on Field-Programmable Gate Arrays (FPGA), Feb 2018."},{"key":"e_1_3_2_1_27_1","first-page":"1","volume-title":"Augmenting HLS with zero-overhead application-specific address mapping for Optane DCPMM,\" in 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Beckwith N.","year":"2022","unstructured":"N. Beckwith, J. Zhang, and J. J. Li, \"Augmenting HLS with zero-overhead application-specific address mapping for Optane DCPMM,\" in 2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 1--9, 2022."},{"key":"e_1_3_2_1_28_1","unstructured":"AMD\/Xilinx \"NVMe host accelerator v1.0 (pb058) \" 2019."},{"key":"e_1_3_2_1_29_1","unstructured":"AMD\/Xilinx \"DMA\/bridge subsystem for PCI Express v4.1 product guide (pg195) \" 2022."},{"key":"e_1_3_2_1_30_1","unstructured":"AMD\/Xilinx \"Alveo U200 and U250 data center accelerator cards data sheet (ds962) \" 2022."},{"key":"e_1_3_2_1_31_1","volume-title":"PCI Express Gen3 switch, 32 lanes, 8 ports","year":"2012","unstructured":"Broadcom, \"PEX8734, PCI Express Gen3 switch, 32 lanes, 8 ports,\" 2012."},{"key":"e_1_3_2_1_32_1","volume-title":"Lawrence Berkeley National Lab.(LBNL)","author":"Luszczek P.","year":"2005","unstructured":"P. Luszczek, J. J. Dongarra, D. Koester, R. Rabenseifner, B. Lucas, J. Kepner, J. McCalpin, D. Bailey, and D. Takahashi, \"Introduction to the HPC challenge benchmark suite,\" tech. rep., Lawrence Berkeley National Lab.(LBNL), Berkeley, CA (United States), 2005."},{"key":"e_1_3_2_1_33_1","unstructured":"AMD\/Xilinx \"Vitis accel examples' repository \" 2021."}],"event":{"name":"FPGA '23: The 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey CA USA","acronym":"FPGA '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543622.3573185","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3543622.3573185","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:00:48Z","timestamp":1750186848000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543622.3573185"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2,12]]},"references-count":33,"alternative-id":["10.1145\/3543622.3573185","10.1145\/3543622"],"URL":"https:\/\/doi.org\/10.1145\/3543622.3573185","relation":{},"subject":[],"published":{"date-parts":[[2023,2,12]]},"assertion":[{"value":"2023-02-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}