{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T03:53:13Z","timestamp":1780372393329,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":46,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,2,12]],"date-time":"2023-02-12T00:00:00Z","timestamp":1676160000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Hong Kong Research Grants Council","award":["General Research Fund (GRF) 16215319"],"award-info":[{"award-number":["General Research Fund (GRF) 16215319"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,2,12]]},"DOI":"10.1145\/3543622.3573188","type":"proceedings-article","created":{"date-parts":[[2023,2,10]],"date-time":"2023-02-10T23:15:13Z","timestamp":1676070913000},"page":"15-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["FADO:\n            <u>F<\/u>\n            loorplan-\n            <u>A<\/u>\n            ware\n            <u>D<\/u>\n            irective\n            <u>O<\/u>\n            ptimization for High-Level Synthesis Designs on Multi-Die FPGAs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3007-4890","authenticated-orcid":false,"given":"Linfeng","family":"Du","sequence":"first","affiliation":[{"name":"Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0390-2320","authenticated-orcid":false,"given":"Tingyuan","family":"Liang","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4532-2017","authenticated-orcid":false,"given":"Sharad","family":"Sinha","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology Goa, Goa, India"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4442-592X","authenticated-orcid":false,"given":"Zhiyao","family":"Xie","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7622-6714","authenticated-orcid":false,"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology, Kowloon, Hong Kong"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,2,12]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45718-6_71"},{"key":"e_1_3_2_1_2_1","first-page":"1","article-title":"Elastic-DF: Scaling performance of DNN inference in FPGA clouds through automatic partitioning","volume":"15","author":"Alonso Tobias","year":"2021","unstructured":"Tobias Alonso, Lucian Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, and Kees Vissers. 2021. Elastic-DF: Scaling performance of DNN inference in FPGA clouds through automatic partitioning. ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 15, 2 (2021), 1--34.","journal-title":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-63465-7_226"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248841"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240838"},{"key":"e_1_3_2_1_6_1","volume-title":"Proceedings 21st International Conference on Computer Design. IEEE, 211--217","author":"Deng Yangdong Steven","year":"2003","unstructured":"Yangdong Steven Deng and Wojciech Maly. 2003. Physical design of the \"2.5 D\" stacked system. In Proceedings 21st International Conference on Computer Design. IEEE, 211--217."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439289"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/2554688.2554776"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541637"},{"key":"e_1_3_2_1_10_1","unstructured":"Xilinx Inc. 2016. UltraRAM: Breakthrough Embedded Memory Integration on UltraScale Devices. https:\/\/docs.xilinx.com\/v\/u\/en-US\/wp477-ultraram"},{"key":"e_1_3_2_1_11_1","unstructured":"Xilinx Inc. 2020a. Vitis High-Level Synthesis User Guide. https:\/\/docs.xilinx.com\/r\/2020.2-English\/ug1399-vitis-hls\/Optimization-Directives"},{"key":"e_1_3_2_1_12_1","unstructured":"Xilinx Inc. 2020b. Vitis High-Level Synthesis User Guide. https:\/\/docs.xilinx.com\/r\/en-US\/ug1399-vitis-hls\/Applying-Optimization-Directives-to-Templates"},{"key":"e_1_3_2_1_13_1","unstructured":"Xilinx Inc. 2020c. Vitis High-Level Synthesis User Guide. https:\/\/docs.xilinx.com\/r\/2020.2-English\/ug1399-vitis-hls\/Automatic-Loop-Pipelining"},{"key":"e_1_3_2_1_14_1","unstructured":"Xilinx Inc. 2022. Floorplanning With Stacked Silicon Interconnect (SSI) Devices. https:\/\/docs.xilinx.com\/r\/en-US\/ug906-vivado-design-analysis\/Floorplanning-With-Stacked-Silicon-Interconnect-SSI-Devices"},{"key":"e_1_3_2_1_15_1","volume-title":"Architecture: Information Processing 92: Proceedings of the IFIP 12th World Computer Congress","volume":"1","author":"Karp Richard M","year":"1992","unstructured":"Richard M Karp. 1992. On-line algorithms versus off-line algorithms: How much is it worth to know the future?. In Algorithms, Software, Architecture: Information Processing 92: Proceedings of the IFIP 12th World Computer Congress, Madrid, Spain, Vol. 1. 416."},{"key":"e_1_3_2_1_16_1","volume-title":"Knapsack Problems","author":"Kellerer Hans","unstructured":"Hans Kellerer, Ulrich Pferschy, and David Pisinger. 2004. The multiple-choice knapsack problem. In Knapsack Problems. Springer, 317--347."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.ipl.2010.05.031"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942136"},{"key":"e_1_3_2_1_19_1","unstructured":"Tomofumi Yuki Louis-Noel Pouchet. 2016. PolyBench\/C. http:\/\/web.cse.ohio-state.edu\/ pouchet.2\/software\/polybench\/"},{"key":"e_1_3_2_1_20_1","volume-title":"Approximation algorithms for bin packing: A survey. Approximation algorithms for NP-hard problems","author":"Jr EG","year":"1996","unstructured":"EG Co man Jr, MR Garey, and DS Johnson. 1996. Approximation algorithms for bin packing: A survey. Approximation algorithms for NP-hard problems (1996), 46--93."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2903025"},{"key":"e_1_3_2_1_22_1","volume-title":"1990 a. Bin-packing problem. Knapsack problems: Algorithms and computer implementations","author":"Martello Silvano","year":"1990","unstructured":"Silvano Martello and Paolo Toth. 1990 a. Bin-packing problem. Knapsack problems: Algorithms and computer implementations (1990), 221--245."},{"key":"e_1_3_2_1_23_1","volume-title":"1990 b. Knapsack problems: algorithms and computer implementations","author":"Martello Silvano","unstructured":"Silvano Martello and Paolo Toth. 1990 b. Knapsack problems: algorithms and computer implementations. John Wiley & Sons, Inc."},{"key":"e_1_3_2_1_24_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 918--923","author":"Meng Pingfan","year":"2016","unstructured":"Pingfan Meng, Alric Althoff, Quentin Gautier, and Ryan Kastner. 2016. Adaptive threshold non-pareto elimination: Re-thinking machine learning for system level design space exploration on FPGAs. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 918--923."},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2478280"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-13731-0_24"},{"key":"e_1_3_2_1_27_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 157--162","author":"Pham Nam Khanh","year":"2015","unstructured":"Nam Khanh Pham, Amit Kumar Singh, Akash Kumar, and Mi Mi Aung Khin. 2015. Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis. In 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 157--162."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3126566","article-title":"COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators","volume":"16","author":"Piccolboni Luca","year":"2017","unstructured":"Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P Carloni. 2017. COSMOS: Coordination of high-level synthesis and memory optimization for hardware accelerators. ACM Transactions on Embedded Computing Systems (TECS), Vol. 16, 5s (2017), 1--22.","journal-title":"ACM Transactions on Embedded Computing Systems (TECS)"},{"key":"e_1_3_2_1_29_1","volume-title":"2018 28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 16--164","author":"Ravishankar Chirag","year":"2018","unstructured":"Chirag Ravishankar, Dinesh Gaitonde, and Trevor Bauer. 2018. Placement strategies for 2.5 D FPGA fabric architectures. In 2018 28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 16--164."},{"key":"e_1_3_2_1_30_1","first-page":"1","article-title":"Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency","volume":"1","author":"Saban Kirk","year":"2011","unstructured":"Kirk Saban. 2011. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx, White Paper, Vol. 1, 1 (2011), 1--10.","journal-title":"Xilinx, White Paper"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3041219"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2009.5158106"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1287\/opre.27.3.503"},{"key":"e_1_3_2_1_34_1","volume-title":"Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks. CoRR","author":"Sohrabizadeh Atefeh","year":"2021","unstructured":"Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, and Jason Cong. 2021. Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks. CoRR, Vol. abs\/2111.08848 (2021). showeprint[arXiv]2111.08848 https:\/\/arxiv.org\/abs\/2111.08848"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3494534"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439292"},{"key":"e_1_3_2_1_37_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 145--150","author":"Wang Zi","year":"2020","unstructured":"Zi Wang, Jianqi Chen, and Benjamin Carrion Schafer. 2020. Efficient and robust high-level synthesis design space exploration through offline micro-kernels pre-characterization. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 145--150."},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/3453688.3461495"},{"key":"e_1_3_2_1_39_1","unstructured":"Xilinx. 2022. Vitis Accelerated Libraries. https:\/\/github.com\/Xilinx\/Vitis_Libraries\/"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.56"},{"key":"e_1_3_2_1_41_1","volume-title":"ScaleHLS: Scalable High-Level Synthesis through MLIR. arXiv preprint arXiv:2107.11673","author":"Ye Hanchen","year":"2021","unstructured":"Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, and Deming Chen. 2021. ScaleHLS: Scalable High-Level Synthesis through MLIR. arXiv preprint arXiv:2107.11673 (2021)."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465827"},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCS.2018.00030"},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702071"},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203809"},{"key":"e_1_3_2_1_46_1","volume-title":"Wenping Wang, and Zhiru Zhang.","author":"Zhou Yuan","year":"2018","unstructured":"Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, and Zhiru Zhang. 2018. Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software-Programmable FPGAs. Int'l Symp. on Field-Programmable Gate Arrays (FPGA) (Feb 2018)."}],"event":{"name":"FPGA '23: The 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","location":"Monterey CA USA","acronym":"FPGA '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543622.3573188","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3543622.3573188","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:00:48Z","timestamp":1750186848000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543622.3573188"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2,12]]},"references-count":46,"alternative-id":["10.1145\/3543622.3573188","10.1145\/3543622"],"URL":"https:\/\/doi.org\/10.1145\/3543622.3573188","relation":{},"subject":[],"published":{"date-parts":[[2023,2,12]]},"assertion":[{"value":"2023-02-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}