{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T07:45:52Z","timestamp":1767771952457,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":42,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,2,12]],"date-time":"2023-02-12T00:00:00Z","timestamp":1676160000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"I\/UCRC Program of the National Science Foundation","award":["1738550"],"award-info":[{"award-number":["1738550"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,2,12]]},"DOI":"10.1145\/3543622.3573191","type":"proceedings-article","created":{"date-parts":[[2023,2,10]],"date-time":"2023-02-10T23:15:13Z","timestamp":1676070913000},"page":"123-133","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoC"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3421-5766","authenticated-orcid":false,"given":"Andrew Elbert","family":"Wilson","sequence":"first","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8364-2970","authenticated-orcid":false,"given":"Nathan","family":"Baker","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5208-1805","authenticated-orcid":false,"given":"Ethan","family":"Campbell","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6583-2869","authenticated-orcid":false,"given":"Jackson","family":"Sahleen","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0328-6713","authenticated-orcid":false,"given":"Michael","family":"Wirthlin","sequence":"additional","affiliation":[{"name":"Brigham Young University, Provo, UT, USA"}]}],"member":"320","published-online":{"date-parts":[[2023,2,12]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Jul","author":"Hamblen M.","year":"2020","unstructured":"M. Hamblen, \"NASA Mars rover Perseverance launches on time Thursday to find evidence of life on Red Planet,\" Retrieved December 26, 2022 from https:\/\/www.fierceelectronics.com\/electronics\/nasa-mars-rover-perseverancelaunches- thursday-to-find-evidence-life-red-planet, Jul 2020."},{"key":"e_1_3_2_1_2_1","volume-title":"5th Annu. Int. Conf. Military Aerosp. Program. Logic Devices, 01","author":"Graham P.","year":"2003","unstructured":"P. Graham, M. Caffrey, J. Zimmerman, D. Eric Johnson, P. Sundararajan, and C. Patterson, \"Consequences and categories of SRAM FPGA configuration SEUs,\" Proc. 5th Annu. Int. Conf. Military Aerosp. Program. Logic Devices, 01 2003."},{"key":"e_1_3_2_1_3_1","first-page":"139","article-title":"An introduction to radiation-induced failure modes and related mitigation methods for Xilinx SRAM FPGAs","author":"Quinn H.","year":"2008","unstructured":"H. Quinn, P. S. Graham, K. Morgan, J. Krone, M. P. Caffrey, and M. J. Wirthlin, \"An introduction to radiation-induced failure modes and related mitigation methods for Xilinx SRAM FPGAs.\" in ERSA, 2008, pp. 139--145.","journal-title":"ERSA"},{"key":"e_1_3_2_1_4_1","article-title":"Neutron radiation testing of multiple TMR soft processors on SRAM-based FPGAs","volume":"2023","author":"Wilson A. E.","year":"2022","unstructured":"A. E. Wilson, M. Wirthlin, and N. Baker, \"Neutron radiation testing of multiple TMR soft processors on SRAM-based FPGAs,\" Accepted to IEEE Transactions on Nuclear Science 2023, August 2022.","journal-title":"Accepted to IEEE Transactions on Nuclear Science"},{"key":"e_1_3_2_1_5_1","first-page":"1","volume-title":"Fault injection of TMR open source RISC-V processors using dynamic partial reconfiguration on SRAM-based FPGAs,\" in 2021 IEEE Space Computing Conference (SCC)","author":"Wilson A. E.","year":"2021","unstructured":"A. E. Wilson and M. Wirthlin, \"Fault injection of TMR open source RISC-V processors using dynamic partial reconfiguration on SRAM-based FPGAs,\" in 2021 IEEE Space Computing Conference (SCC), 2021, pp. 1--8."},{"key":"e_1_3_2_1_6_1","volume-title":"NASA SpaceCube intelligent multi-purpose system for enabling remote sensing, communication, and navigation in mission architectures,\" in Small Satellite Conference","author":"Brewer C.","year":"2020","unstructured":"C. Brewer, N. Franconi, R. Ripley, A. Geist, T. Wise, S. Sabogal, G. Crum, S. Heyward, and C. Wilson, \"NASA SpaceCube intelligent multi-purpose system for enabling remote sensing, communication, and navigation in mission architectures,\" in Small Satellite Conference 2020, no. SSC20-VI-07, 2020."},{"volume-title":"Analysis of the critical bits of a RISC-V processor implemented in an SRAM-based FPGA for space applications,\" Electronics (Switzerland)","author":"Aranda L. A.","key":"e_1_3_2_1_7_1","unstructured":"L. A. Aranda, N. J. Wessman, L. Santos, A. S\u00e1nchez-Maci\u00e1n, J. Andersson, R. Weigand, and J. A. Maestro, \"Analysis of the critical bits of a RISC-V processor implemented in an SRAM-based FPGA for space applications,\" Electronics (Switzerland), vol. 9, no. 1, 2020."},{"key":"e_1_3_2_1_8_1","first-page":"319","volume-title":"The case for RISC-V in space,\" in International Conference on Applications in Electronics Pervading Industry","author":"Mascio S. D.","year":"2018","unstructured":"S. D. Mascio, A. Menicucci, G. Furano, C. Monteleone, and M. Ottavi, \"The case for RISC-V in space,\" in International Conference on Applications in Electronics Pervading Industry, Environment and Society. Springer, 2018, pp. 319--325."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.2514\/1.I010735"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2020.2995729"},{"key":"e_1_3_2_1_11_1","volume-title":"Polytech. Turin","author":"Minnella F.","year":"2018","unstructured":"F. Minnella, \"Protection and characterization of an open source soft core against radiation effects.\" Ph.D. dissertation, Polytech. Turin, 2018."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/MAES.2017.160182"},{"key":"e_1_3_2_1_13_1","volume-title":"an opensource SoC builder and library based on Migen Python DSL,\" in OSDA","author":"Kermarrec F.","year":"2019","unstructured":"F. Kermarrec, S. Bourdeauducq, H. Badier, and J.-C. Le Lann, \"Litex: an opensource SoC builder and library based on Migen Python DSL,\" in OSDA 2019, colocated with DATE 2019 Design Automation and Test in Europe, 2019."},{"key":"e_1_3_2_1_14_1","unstructured":"SpinalHDL \"VexRiscv \" Retrieved December 26 2022 from https:\/\/github.com\/ SpinalHDL\/VexRiscv."},{"key":"e_1_3_2_1_15_1","unstructured":"SpinalHDL \"SpinalHDL \" Retrieved December 26 2022 from https:\/\/github.com\/ SpinalHDL\/SpinalHDL."},{"key":"e_1_3_2_1_16_1","unstructured":"LiteX-Hub \"Linux on LiteX VexRiscv \" Retrieved February 3 2022 from https: \/\/github.com\/litex-hub\/linux-on-litex-vexriscv."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"crossref","unstructured":"M. J. Wirthlin A. M. Keller C. McCloskey P. Ridd D. Lee and J. Draper \"SEU mitigation and validation of the LEON3 soft processor using triple modular redundancy for space processing \" in Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays 2016 pp. 205--214.","DOI":"10.1145\/2847263.2847278"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2636574"},{"key":"e_1_3_2_1_19_1","first-page":"165","volume-title":"Oct 2014","author":"Psarakis M.","unstructured":"M. Psarakis, A. Vavousis, C. Bolchini, and A. Miele, \"Design and implementation of a self-healing processor on SRAM-based FPGAs,\" in 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2014, pp. 165--170."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2635028"},{"key":"e_1_3_2_1_21_1","volume-title":"dissertation","author":"Rollins N. H.","year":"2012","unstructured":"N. H. Rollins, \"Hardware and software fault-tolerance of softcore processors implemented in SRAM-based FPGAs,\" Ph.D. dissertation, Brigham Young University, Provo, UT, USA, 2012, aAI3506158."},{"key":"e_1_3_2_1_22_1","first-page":"683","volume-title":"Aug 2012","author":"Hong C.","unstructured":"C. Hong, K. Benkrid, X. Iturbe, and A. Ebrahim, \"Design and implementation of fault-tolerant soft processors on FPGAs,\" in 22nd International Conference on Field Programmable Logic and Applications (FPL), Aug 2012, pp. 683--686."},{"key":"e_1_3_2_1_23_1","first-page":"1036","volume-title":"Control and Computing Technologies","author":"Safarulla I. M.","year":"2014","unstructured":"I. M. Safarulla and K. Manilal, \"Design of soft error tolerance technique for FPGA based soft core processors,\" in 2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies, May 2014, pp. 1036--1040."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3169495"},{"key":"e_1_3_2_1_25_1","volume-title":"Xilinx","author":"Modular Microblaze Triple","year":"2022","unstructured":"Microblaze Triple Modular Redundancy (TMR) Subsystem v1.0, Retrieved December 26, 2022 from https:\/\/www.xilinx.com\/support\/documentation\/ip_ documentation\/tmr\\\/v1_0\/pg268-tmr.pdf, Xilinx, 2018."},{"key":"e_1_3_2_1_26_1","first-page":"47","volume-title":"May","author":"Ichinomiya Y.","year":"2010","unstructured":"Y. Ichinomiya, S. Tanoue, M. Amagasaki, M. Iida, M. Kuga, and T. Sueyoshi, \"Improving the robustness of a softcore processor against SEUs by using TMR and partial reconfiguration,\" in 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, May 2010, pp. 47--54."},{"key":"e_1_3_2_1_27_1","volume-title":"Netlist analysis and transformations using SpyDrNet,\" in Proceedings of the Python in Science Conference","author":"Skouson D.","year":"2020","unstructured":"D. Skouson, A. Keller, and M. Wirthlin, \"Netlist analysis and transformations using SpyDrNet,\" in Proceedings of the Python in Science Conference, 2020."},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2302432"},{"key":"e_1_3_2_1_29_1","first-page":"1","volume-title":"Single-event characterization of the 28 nm Xilinx Kintex-7 field-programmable gate array under heavy ion irradiation,\" in 2014 IEEE Radiation Effects Data Workshop (REDW)","author":"Lee D. S.","year":"2014","unstructured":"D. S. Lee, M. Wirthlin, G. Swift, and A. C. Le, \"Single-event characterization of the 28 nm Xilinx Kintex-7 field-programmable gate array under heavy ion irradiation,\" in 2014 IEEE Radiation Effects Data Workshop (REDW), 2014, pp. 1--5."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.13182\/NSE90-A27471"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"crossref","unstructured":"M. Berg C. Poivey D. Petrick D. Espinosa A. Lesea K. LaBel M. Friendlich H. Kim and A. Phan \"Effectiveness of internal vs. external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design test and analysis \" in 2007 9th European Conference on Radiation and Its Effects on Components and Systems 2007 pp. 459--466.","DOI":"10.1109\/RADECS.2007.5205603"},{"key":"e_1_3_2_1_32_1","first-page":"218","volume-title":"Sep. 2016","author":"Gruwell A.","unstructured":"A. Gruwell, P. Zabriskie, and M. Wirthlin, \"High-speed FPGA configuration and testing through JTAG,\" in 2016 IEEE AUTOTESTCON, Sep. 2016, pp. 218--225."},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2021.3068835"},{"key":"e_1_3_2_1_34_1","volume-title":"dissertation","author":"Perez-Celis J. A.","year":"2021","unstructured":"J. A. Perez-Celis, \"Statistical method for extracting radiation-induced multi-cell upsets and anomalies in SRAM-Based FPGAs,\" Ph.D. dissertation, Brigham Young University, Provo, UT, USA, 2021."},{"key":"e_1_3_2_1_35_1","first-page":"112","volume-title":"Analysis of SEU effects in a pipelined processor,\" in Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW","author":"Rebaudengo M.","year":"2002","unstructured":"M. Rebaudengo, M. Sonza Reorda, and M. Violante, \"Analysis of SEU effects in a pipelined processor,\" in Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), 2002, pp. 112--116."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"crossref","unstructured":"M. Barbirotta A. Mastrandrea F. Menichelli F. Vigli L. Blasi A. Cheikh S. Sordillo F. Di Gennaro and M. Olivieri \"Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment \" in 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2020 pp. 1--6.","DOI":"10.1109\/DFT50435.2020.9250871"},{"key":"e_1_3_2_1_37_1","first-page":"237","volume-title":"Analysis of a fault tolerant edge-computing microarchitecture exploiting vector acceleration,\" in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","author":"Barbirotta M.","year":"2022","unstructured":"M. Barbirotta, A. Cheikh, A. Mastrandrea, F. Menichelli, and M. Olivieri, \"Analysis of a fault tolerant edge-computing microarchitecture exploiting vector acceleration,\" in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022, pp. 237--240."},{"key":"e_1_3_2_1_38_1","unstructured":"BYUCCL \"Bitstream fault analysis tool \" Retrieved December 26 2022 from https:\/\/github.com\/byuccl\/bfat."},{"key":"e_1_3_2_1_39_1","unstructured":"F4PGA \"Project X-Ray \" Retrieved September 9 2022 from https:\/\/github.com\/ f4pga\/prjxray."},{"key":"e_1_3_2_1_40_1","first-page":"174","volume-title":"Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs,\" in 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS)","author":"Sterpone L.","year":"2017","unstructured":"L. Sterpone and L. Boragno, \"Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs,\" in 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), 2017, pp. 174-- 179."},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2019.2956473"},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2877579"}],"event":{"name":"FPGA '23: The 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Monterey CA USA","acronym":"FPGA '23"},"container-title":["Proceedings of the 2023 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543622.3573191","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3543622.3573191","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:00:48Z","timestamp":1750186848000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543622.3573191"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2,12]]},"references-count":42,"alternative-id":["10.1145\/3543622.3573191","10.1145\/3543622"],"URL":"https:\/\/doi.org\/10.1145\/3543622.3573191","relation":{},"subject":[],"published":{"date-parts":[[2023,2,12]]},"assertion":[{"value":"2023-02-12","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}